Using ScaLAPACK and Cluster FFT on Intel Xeon Phi Coprocessors

Intel MKL ScaLAPACK and Cluster FFT support only Intel MPI Library on Intel Xeon Phi coprocessors.

The Intel MPI library can treat each Intel Xeon Phi coprocessor as a regular node in a cluster of processors based on Intel 64 architecture and Intel Xeon Phi coprocessors and enables a straightforward way to run an MPI application on clusters that contain both processors and coprocessors as compute nodes.

The documentation for the Intel MPI library recommends the following steps to run an MPI application on the specific Intel Xeon Phi coprocessor and the host node if the nodes are properly specified on the cluster and the network protocols and environment are properly set up:

  1. Build the application for the Intel 64 architecture.

  2. Build the application for the Intel MIC Architecture.

  3. Launch the application from the host computer.


If you need to run the application on the coprocessor only, you can alternatively launch it from the coprocessor.

For more details, check the Intel MPI Library documentation, available in the Intel Software Documentation Library.

To run a dynamically linked application natively, perform the Scripts to Set Environment Variables Setting Environment Variables step of the Getting Started process. In addition to other environment variables, it sets:

  • LD_LIBRARY_PATH to contain <mkl directory>/lib/intel64

  • MIC_LD_LIBRARY_PATH to contain <mkl directory>/lib/mic

When building your application that uses Intel MKL ScaLAPACK or Cluster FFT, follow the linking guidelines in the Linking with ScaLAPACK and Cluster FFTs, but be aware that only Intel compiler and Intel MPI are supported, and only Intel threading layer is provided for Intel MKL. You can find a full list of Intel MKL libraries for Intel MIC architecture in Detailed Directory Structure of the lib mic Directory. Be aware that coprocessors run a Unix* operating system.


Use the Using the Link-line Advisor to quickly choose the appropriate set of libraries and linker options.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

For more complete information about compiler optimizations, see our Optimization Notice.