Instruction pipelining

Instruction pipelining

Hi...

Is there any option of getting  number of instructions that are being executed per cycle in INTEL Platform.

I am currently using below configurations

1) Intel i7 SandyBridge Architecture with Windows OS

 2) Visual Studio 2010

Thanks in Advance.

Regards,

Kiran

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For more complete information about compiler optimizations, see our Optimization Notice.

On the face of it, what you're asking for is a default result of VTune profiling (in a sample-averaged sense).  Maybe you haven't made your question clear.

Judging by your question you need low level profiling tool like Intel VTune.

> ...getting  number of instructions that are being executed per cycle...

I guess that you want IPC (instructions per clycles), VTune(TM) Amplifier XE already provide CPI (Cycles per instruction) average data for function / module - if you use Advanced-hotspots analysis. Thus, IPC = 1 / CPI is what you want.

> Intel i7 SandyBridge Architecture with Windows OS

Normally CPI data range is [0.25 - 1] for integer code sequence, it means IPC data range is [1 - 4], I think 

> Thanks for all the replies.

Although Intel Vtune profiler (or) Amplifier provides CPI.

My point was, as a part of Optimisationt to anlayze those blocking instructions which stops compiler from being parallelised.

There is also cycles  per machine code instruction and instruction throughput the throughput is more related to pipeline that means after how many clock cycles second instruction can be executed.Some instructions needs many cycles to be executed fore example division or trigonometric instructions.

>  as a part of Optimisationt to anlayze those blocking instructions which stops compiler from being parallelised.

Advanced processor will reorder of instructionn sequence to avoid pipe line stall. Usually it looks like register resource dependency in nearest two instruction. Maybe compiler also will optimize it. VTune(TM) Amplifier XE does not display such info, only provides performance data annotated with source line. You may check source view in assembly to verify if instructions are blocked in pipe line, but as I told you before, recent processor has reodering capbility...

 You may check source view in assembly to verify if instructions are blocked in pipe line, but as I told you before, recent processor has reodering capbility...

>> I have generated assembly code from vcc compiler (.cod file). It clearly shows how many assembly instructions are executed for each line of C code, but there is no option of Knowing which among them will execute in parallel :)

>> I have generated assembly code from vcc compiler (.cod file). It clearly shows how many assembly instructions are executed for each line of C code, but there is no option of Knowing which among them will execute in parallel :)

There is no such function to display "indicator" ("!") in problematical instructions which may cause stall in pipeline.

 Only CPU time was annotated on instruction in report. 

IIRC  reordering of instruction or out of order execution was already present in Pentium 3 and maybe in Alfa CPU.As it was told you can look at assembly code and try to guess which instruction can be blocking.For example some kind of interdependencies can be present in complex arithmetics composed from many dependent variables and internally CPU will use register renaming  to effectively execute such a code.Another example of non blocking execution can be a loop control statements integer in nature and it will be executed in parallel to loop block statements.Moreover ALU logic can pipeline various arithmetic and logical operations on various instructions and this is a base to calculate instruction tthroughput.

Thanks for all your response iliyapolak and Peter Wang (Intel).

You are welcome kiran.

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