Overview: Heterogeneous Programming

This topic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).

About Heterogeneous Programming

The compiler includes language extensions that simplify writing parallel programs that can offload sections to run on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture).

Execution begins on the host CPU and, based on user-defined code, some sections are offloaded to the coprocessor.

Heterogeneous programming must deal with two differences from traditional CPU programming:

  • The instruction sets on the CPU and the coprocessor are similar, but not identical.

  • The host CPU and the coprocessor do not share common system memory.

Programming Models

The compiler supports the following programming models, which differ in their approach to dealing with the lack of shared system memory:

  • A non-shared memory model.

    This model uses the pragma offload, and other pragmas with the prefix offload_.

    This model is appropriate for dealing with flat data structures such as scalars, arrays and structs that are bit-wise copyable.

    Data in this model is copied back and forth between the CPU and the coprocessor around regions of offloaded code. The data selected for transfer is a combination of variables implicitly transferred because they are lexically referenced within offload constructs, and variables explicitly listed in clauses in the pragma.

  • A virtual-shared memory model.

    This model uses _Cilk_shared and _Cilk_offload keywords.

    This model is appropriate for dealing with complex pointer-based data structures, such as linked lists, trees and the like.

    This model uses a software implementation of virtual memory that is shared between the CPU and the coprocessor. You either declare data to be exchanged during offloads as shared, or if the data is dynamic, it is allocated using special alloc and free calls.

You can use both models of offloading in a single program. However, the data manipulated by the two models should be distinct.

In both models, specifying that a construct should run on the coprocessor does not guarantee that it will. The presence of an Intel® MIC Architecture-based subsystem and its availability at the offload point determines if the offload succeeds. When an offload fails, the program exits with an error message.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

For more complete information about compiler optimizations, see our Optimization Notice.