This topic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).
Memory synchronization between the CPU and the target occurs at the following predefined points:
when an offloaded function is called by the CPU, and upon entering the offloaded function on the target
when an offloaded function on the target returns, and upon the return of the function to the CPU
Currently no other synchronization points exist, so any simultaneous access to the shared memory location between the predefined points is treated as a race condition, and the behavior is undefined.