Using the Intel® Compiler for Intel® Quark™ Microcontrollers, you can compile and generate applications that can run on IA-32 architectures.
The microcontroller (MCU) compiler in Intel System Studio for Microcontrollers (ISSM) has a Clang front end, and an LLVM middle and backend. The target is baremetal and Wind River* Zephyr* micro-kernels and nano-kernels.
This compiler runs on an Intel® 64 architecture-based host system running Windows* and Linux* operating systems. You can use the compiler to compile and generate applications that can run on IA-32 architectures. The compiler has support for the MCU software application binary interface (ABI), which has been published externally.
The Clang front end is compatible with GCC such that you can use the same command to build code with gcc or the Intel® Compiler for Intel® Quark™ Microcontrollers.
The Intel® Compiler for Intel® Quark™ Microcontrollers:
Is tuned for code size, because the MCU device memory is very small. The options of interest are –Os (code-size) and –O2 (performance).
Includes support for attributes.
No libraries are provided with this compiler, it leverages the libraries provided along with the gcc compiler toolchain in ISSM, including:
libgcc (gcc’s FP library)
libc (C runtime library modified to be BSD 3 compliant)
libgloss (for Linux)
libm (math) with gcc for MCU.
an optimized fp library called libsoftp which is a subset of libgcc and libimf (subset math library)
Developer and User Information for Clang
The comprehensive documentation located at http://clang.llvm.org/docs/ describes how to use the Clang compiler and provides complete information on supported language extensions.
This guide describes the features, options, and functionality introduced by Intel to extend the Clang-front-end for C++ compiler features described at http://clang.llvm.org/docs/.
You can find the Clang Compiler User’s Manual at http://clang.llvm.org/docs/UsersManual.html.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804