Module Board-to-Board Connector Pinout

The Intel® Joule™ module interfaces with the expansion board through two high-density, board-to-board connectors labeled J6 and J7 on the expansion board. The default pin usage of J6 and J7 refers to the vantage point of the expansion board. For example the +VBUS signal originates in the expansion board and is delivered to the module; therefore, +VBUS is an output from the expansion board.

Unless otherwise noted, all I/O signals operate at 1.8 VDC (with the exception of industry standard buses and protocols) each of which must operate within their defining specification parameters.

Module J6 Connector Interface

Pin

Signal Name

Default Usage

Description

41

+V5P0V_VCONN

Output

Power for USB 3.0 CC pins for VCONN-powered accessory

99

VBUS_SENSE

Output

Connected to +VBUS from USB for PMIC detection when USB power source is plugged in

37

VDCIN_SENSE

Output

Connected to +VDC_IN from DC jack for PMIC detection when DC jack is plugged in.

36

+VDD1

Input

System 1.8 VDC

30

+VDD3

Input

System 3.3 VDC

11

+VRTC

Output

Real-time clock backup battery input to PMIC

2, 5, 7, 12, 15, 17

+VSYS

Output

System power

84

BTN_N

Output

Intended for a general purpose (button or signal) that interrupts the processor to perform a priority task or execute a contextually based routine, this input is read at GPIO_17 and driven by a user action, sensor, or subsystem.

71

CLK_19P2M

Input

19.2 MHz clock

43

CODEC_MCLK

Input

MCLK for Master Mode operation of I2S audio

68

DDI1_CTRL_CLK

Input

HDMI I2C clock

70

DDI1_CTRL_DAT

Input/Output

HDMI I2C data

4, 10, 19, 42, 48, 54, 60, 66, 72, 73, 82, 86, 96, 98, 100

GND

Ground

System ground

94

GPIO_22

Output

General purpose input/output

46

HDMI_CLK_DN

Input

HDMI clock negative

44

HDMI_CLK_DP

Input

HDMI clock positive

62

HDMI_TX_0_DN

Input

HDMI data lane 0 negative

64

HDMI_TX_0_DP

Input

HDMI data lane 0 positive

58

HDMI_TX_1_DN

Input

HDMI data lane 1 negative

56

HDMI_TX_1_DP

Input

HDMI data lane 1 positive

50

HDMI_TX_2_DN

Input

HDMI data lane 2 negative

52

HDMI_TX_2_DP

Input

HDMI data lane 2 positive

65

HPD_SRC

Output

General purpose input/output for HDMI cable hot-plug detection

This signal sets up a start-up communication between sources and sink HDMI devices; this is also connected to GPIO_200.

57

I2C_0_SCL

Input

I2C port 0 clock, used for configuration EEPROM

95

I2C_0_SDA

Input/Output

I2C port 0 data, used for configuration EEPROM

39

I2S_1_CLK

Input/Output

I2S-bit clock supplied by the module in master mode and serves as an input in slave mode.

45

I2S_1_FS

Input

I2S frame sync

47

I2S_1_RXD

Output

I2S receive data

49

I2S_1_TXD

Input

I2S transmit data

25

ISH_GPIO_0

Input

General purpose input/output 0, set at output by BIOS until reconfigured1

27

ISH_GPIO_1

Input

General purpose input/output 1, set at output by BIOS until reconfigured1

32

ISH_GPIO_2

Input

General purpose input/output 2, set at output by BIOS until reconfigured1

34

ISH_GPIO_3

Input

General purpose input/output 3, set at output by BIOS until reconfigured1

29

ISH_GPIO_4

Input

General purpose input/output 4

38

ISH_GPIO_5

Input

General purpose input/output 5

31

ISH_GPIO_6

Input

General purpose input/output 6

16

ISH_I2C_0_SCL

Input

I2C port 0 clock, mapped to I2C5

18

ISH_I2C_0_SDA

Input/Output

I2C port 0 data, mapped to I2C5

21

ISH_I2C_1_SCL

Input

I2C port 1 clock, mapped to I2C6

23

ISH_I2C_1_SDA

Input/Output

I2C port 1 data, mapped to I2C6

69

OTG_EN

Input

Module generates the OTG enable signal based on the detected port connection.

9

PMIC_PWRBTN_N

Output

Active low output from the expansion board to the module that controls the power state of the module and, by extension, the expansion board, see Power Delivery, Signaling, and Reset for how the PMIC_PWRBTN_N signal controls the module power state based on duration of the low signal.

33

PMIC_PWRGOOD

Input

Active high output signal from the module to the expansion board that latches the state of the module strapping options (refer to Section 4.6), this signal also indicates if +VDD1 and +VDD3 power supplies from the module are within specification.

13

PMIC_RESET_N

Input

Active low signal output from the module to the expansion board, an expansion board may use this signal to control when the module strapping option signals are driven by the expansion board circuitry. Refer to Power Delivery, Signaling, and Reset for additional details of the PMIC_RESET_N signal.

Leave the PMIC_RESET_N signal floating if not used on the expansion board.

1

PWM_0

Input

Programmable pulse width modulator port 0

3

PWM_1

Input

Programmable pulse width modulator port 1

22

PWM_2

Input

Programmable pulse width modulator port 2

24

PWM_3

Input

Programmable pulse width modulator port 3

40

Reserved

N/A

No connect

35

Reserved

N/A

No connect

92

VBATT_SENSE

Output

Senses when battery is plugged in

79

SDCARD_CD_N

Output

SD card detect, active low when a card is present, pulled high with internal pull-up when a card is not present

75

SDCARD_CLK

Input

SD card clock

89

SDCARD_CMD

Input/Output

SD card command is used for card initialization and transfer of commands.

81

SDCARD_D0

Input/Output

SD card data 0, by default, during power up or reset, only data 0 is used for data transfer.

83

SDCARD_D1

Input/Output

SD card data 1

85

SDCARD_D2

Input/Output

SD card data 2

87

SDCARD_D3

Input/Output

SD card data 3

77

SDCARD_LVL_CLK_FB

Output

SD card-clock feedback for aligning the SDIO data from the level shifter on-board the expansion board through the controller, there is a loopback through the SD card level shifter that drives this pin.

90

SDCARD_LVL_CMD_DIR

Input

SD card-command direction indicates if the host is transmitting or receiving over the command pin.

67

SDCARD_LVL_DAT_DIR

Input

SD card-data direction indicates if the host is transmitting or receiving over the data.

88

SDCARD_LVL_SEL

Input

SD card-level select performs the 1.8 V-to-3.0 V negotiation.

91

SDCARD_PWR_DOWN_N

Input

SD card-power down tells the SDIO device to power down.

53

SPI_1_CLK

Input

SPI port 1 clock

55

SPI_1_FS0

Input

SPI port 1 slave select 0

14

SPI_1_FS2

Input

SPI port 1 slave select 2, hardware strap with disable boot from SD card functionality

63

SPI_1_MISO

Output

SPI port 1 receive data.

51

SPI_1_MOSI

Input

SPI port 1 transmit data

93

UART_0_TXD

Input

UART port 0 transmit data, hardware strap with reserved functionality
Note: This goes with UART0 signals on other connector.

26

UART_1_RXD

Output

UART port 1 receive data.

28

UART_1_TXD

Input

UART port 1 transmit data, hardware strap with disable boot from eMMC functionality

74

UART2_CTS

Output

BIOS configures the UART port 2 lines as the serial debug path. See UART Interfaces for details.

76

UART2_RTS

Input

BIOS configures the UART port 2 lines as the serial debug path. See UART Interfaces for details..

80

UART2_RXD

Output

BIOS configures the UART port 2 lines as the serial debug path. See UART Interfaces for details..

78

UART2_TXD

Input

BIOS configures the UART port 2 lines as the serial debug path. See UART Interfaces for details..

59

USB_TYPC_CC1

Input/Output

Type-C configuration channel 1, connected to PMIC CC channel 1 pin

61

USB_TYPC_CC2

Input/Output

Type-C configuration channel 2, connected to PMIC CC channel 2 pin

8

USB2_0_DN

Bidirectional

USB 2.0 port 0 data negative, connected to PMIC USB 2.0 port 0

6

USB2_0_DP

Bidirectional

USB 2.0 port 0 data positive, connected to PMIC USB 2.0 port 0

20

USB2_ID_PMIC

Output

USB OTG ID for device attach or detach and USB ACA detection through detection of resistance connected to pin, connected to PMIC USBID pin

97

VCONN_DCDC_EN

Input

VCONN_DCDC_EN is a control signal generated by the module to enable expansion board-based supply for USB 3.0 CC pins.

  1. During BIOS execution the ISH_GPIO_0-3 signals are configured as outputs and change state to indicate BIOS progression. End users should take this into account in their design.

Module J7 Connector Interface

Pin

Signal Name

Default Usage

Description

1, 3, 20, 22, 32, 34

+VSYS

Output

System power

52

AVS_M_CLK_A1

Input

Microphone clock for channel A (voice trigger microphone)

62

AVS_M_CLK_B1

Input

Microphone clock for channel B (secondary microphone)

66

AVS_M_DATA_1

Output

Microphone data for channels A and B

73

FLASH_RST_N

Input

Although titled FLASH_RST_N, function is configured as GPIO functionality

75

FLASH_TORCH

Input

Although titled FLASH_TORCH, function is configured as GPIO functionality

71

FLASH_TRIGGER

Input

Although titled FLASH_TRIGGER, function is configured as GPIO functionality

2, 5, 8, 10, 16, 17, 23, 24, 29, 30, 35, 36, 41, 42, 54, 60, 61, 67, 74, 80, 84, 85, 91, 90, 93, 96, 99

GND

Ground

System ground

43

I2C_1_SCL

Input

I2C port 1 clock

45

I2C_1_SDA

Input/Output

I2C port 1 data

28

I2C_2_SCL

Input

I2C port 2 clock

26

I2C_2_SDA

Input/Output

I2C port 2 data

9

ISH_UART_0_CTS

Output

Although titled UART, function is configured as GPIO functionality

11

ISH_UART_0_RTS

Input

Although titled UART, function is configured as GPIO functionality

13

ISH_UART_0_RXD

Output

Although titled UART, function is configured as GPIO functionality

15

ISH_UART_0_TXD

Input

Although titled UART, function is configured as GPIO functionality

7

PMIC_SLPCLK_1

Input

32.768 kHz RTC

68

Reserved

N/A

No connect

82

Reserved

N/A

No connect

27

Reserved

N/A

No connect

25

Reserved

N/A

No connect

21

Reserved

N/A

No connect

19

Reserved

N/A

No connect

33

Reserved

N/A

No connect

31

Reserved

N/A

No connect

39

Reserved

N/A

No connect

37

Reserved

N/A

No connect

76

Reserved

N/A

No connect

78

Reserved

N/A

No connect

12, 14, 38, 40, 69, 81, 83, 92,
94, 98,
100

Reserved

N/A

No connect

56

Reserved

N/A

No connect

58

Reserved

N/A

No connect

64

Reserved

N/A

No connect

88

Reserved

N/A

No connect

86

Reserved

N/A

No connect

50

Reserved

N/A

No connect

72

Reserved

N/A

No connect

70

Reserved

N/A

No connect

59

SPI_0_CLK

Input

SPI port 0 clock

77

SPI_0_FS0

Input

SPI port 0 chip select 0, hardware strap with reserved functionality

79

SPI_0_FS1

Input

SPI port 0 chip select 1

53

SPI_0_FS2

Input

SPI port 0 chip select 2

49

SPI_0_MISO

Output

SPI port 0 receive data

57

SPI_0_MOSI

Input

SPI port 0 transmit data

47

UART_0_CTS

Output

UART port 0 clear-to-send

55

UART_0_RTS

Input

UART port 0 return-to-send

51

UART_0_RXD

Output

UART port 0 receive data (Note: UART_0_TXD is on the J6 connector)

63

USB2_1_DN

Bidirectional

USB 2.0 port 1 data negative

65

USB2_1_DP

Bidirectional

USB 2.0 port 1 data positive

44

USB3_0_RX_DN

Output

USB 3.0 port 0 data receive negative

46

USB3_0_RX_DP

Output

USB 3.0 port 0 data receive positive

6

USB3_0_TX_DN

Input

USB 3.0 port 0 data transmit negative

4

USB3_0_TX_DP

Input

USB 3.0 port 0 data transmit positive

97

USB3_1_RX_DN

Output

USB 3.0 port 1 data receive positive

95

USB3_1_RX_DP

Output

USB 3.0 port 1 data receive negative

89

USB3_1_TX_DN

Input

USB 3.0 port 1 data transmit negative

87

USB3_1_TX_DP

Input

USB 3.0 port 1 port 1 data transmit positive

18

USBC_SEL

Input

PMIC mux control for Type-C polarity

 

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