Power On Timing Sequence (cold boot)

 

This power good signal transitions HIGH after the VDD1 and VDD3 supplies are within specification.  Expansion board and mezzanine board designs must ensure that circuitry does not interfere with the state of the compute module boot strap pins.  See Boot Strap Signal Isolation for an example isolation circuit.

All rails are off within 2 milliseconds of a power off event.

Power up order of rails +VDD1 and +VDD3 is not guaranteed, but does not adversely affect operability.

 

For more complete information about compiler optimizations, see our Optimization Notice.