SPI Interface

The expansion board routes two SPI interfaces from the module, through a level translator to convert the module 1.8 V logic levels to those required by the breakout board. The breakout board should include appropriate pullup values to the desired voltage, but not to exceed 3.3 V.

SPI mapping to breakout connectors

Pin #

Signal Name

Direction at Breakout Connector

Signal Description

J13.25

SPI_0_CLK_LS

Input

SPI port 0 Clock

J13.19

SPI_0_FS0_LS

Input

SPI port 0 slave select 0

J13.21

SPI_0_FS1_LS

Output

SPI port 0 chip select 1

J13.23

SPI_0_FS2_LS

Output

SPI port 0 chip select 2

J13.29

SPI_0_MISO_LS

Output

SPI port 0 receive data

J13.27

SPI_0_MOSI_LS

Input

SPI port 0 transmit data

J12.10

SPI_1_CLK_LS

Output

SPI port 1 Clock

J12.6

SPI_1_FS0_LS

Output

SPI port 1 slave select 0

J12.8

SPI_1_FS2_LS

Output

SPI port 1 slave select 2, hardware strap with disable boot from SD card functionality

J12.2

SPI_1_MISO_LS

Input

SPI port 1 receive data

J12.4

SPI_1_MOSI_LS

Output

SPI port 1 transmit data

SPI Level Transitions

All of the SPI interface lines are level transitioned (shifted) between the breakout connector 3.3 VDC levels and the Intel Joule compute module, which operates at 1.8 VDC levels.

Level translation is performed by a Texas Instruments* LSF0108RKSR open drain translator.

The expansion board uses a 200 kΩ pullup resistor from the +V3P3V supply to enable EU17 when the expansion board is active.

SPI Strapping for SD Card Boot

To force the expansion board to boot from SD card, the FS2 signal of SPI port 1 is pulled low by strapping J14 Pin 2 and 4.

Additional boot-mode configuration by hardware strapping is covered in Boot Option Jumpers located in Buttons Jumpers and LEDs.

SPI Signal Termination and Conditioning

For information about signal termination and conditioning, definitions of the values in the following table, and how the values were measured, refer to Termination and Conditioning. For an example of how to wire a pullup resistor for a 3.3 V pullup voltage, refer to GPIO Signal Termination and Conditioning

SPI signal level translation termination recommendations

Signal Name

Pullup Voltage

Rmin (Ω)

CLOAD (pF)

Trise (ns)

Tfall (ns)

SPI_0_CLK_LS

SPI_0_FS0_LS

SPI_0_FS1_LS

SPI_0_FS2_LS

SPI_0_MISO_LS

SPI_0_MOSI_LS

SPI_1_CLK_LS

SPI_1_FS0_LS

SPI_1_FS2_LS

SPI_1_MISO_LS

SPI_1_MOSI_LS

3.3

1100

22

33

17

 

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