Default BIOS Pinmapping

Pinmapping for the breakout connectors can be found in Module Board-to-Board Connector Pinout. The tables below provides the pin assignment, signal name, and description for the signals on the breakout connectors J12 and J13. The default breakout usage refers to the vantage point of the expansion board. For example, the SPI_1_MISO_LS signal originates in the breakout board and is delivered to the expansion board, therefore it is an input.

These signals are mapped by various operating systems in different ways. The tables below depicts power-on and default BIOS only.

Breakout Connector J12

J12 Pin

Signal Description

Default
Breakout
Usage

Net Name at Breakout

Module
Pin

1

General purpose input/output

GPIO

GPIO_22_LS

J2.94

2

SPI port 1 receive data.

Output

SPI_1_MISO_LS

J2.63

3

Active low output from the expansion board to the module that controls the power state of the module and, by extension, the expansion board, see Power Delivery, Signaling, and Reset for how the PMIC_PWRBTN_N signal controls the module power state based on duration of the low signal.

GPIO

PMIC_RESET_N_LS

J2.13

4

SPI port 1 transmit data

Input

SPI_1_MOSI_LS

J2.51

5

19.2 MHz clock

Output

CLK_19P2M_LS

J2.71

6

SPI port 1 slave select 0

Input

SPI_1_FS0_LS

J2.55

71

UART port 0 transmit data, hardware strap with reserved functionality (see note 1 below)

Input

UART_0_TXD_LS

J3.93

8

SPI port 1 slave select 2, hardware strap with disable boot from SD card functionality

Output

SPI_1_FS2_LS

J2.14

9

Active high output signal from the module to the expansion board that latches the state of the module strapping options. This signal also indicates if +VDD1 and +VDD3 power supplies from the module are within specification.

Reserved

PMIC_PWRGOOD_LS

J2.33

10

SPI port 1 clock

Input

SPI_1_CLK_LS

J2.53

11

I2C port 0 data, for optional expansion board EEPROM device

Bidirectional

I2C_0_SDA_LS

J2.95

12

I2S receive data

Output

I2S_1_RXD_LS

J2.47

13

I2C port 0 clock, for optional expansion board EEPROM device

Input

I2C_0_SCL_LS

J2.57

14

I2S transmit data

Input

I2S_1_TXD_LS

J2.49

15

I2C port 0 data, mapped to I2C5

Bidirectional

ISH_I2C_0_SDA_LS

J2.18

16

I2S frame sync

Input

I2S_1_FS_LS

J2.45

17

I2C port 0 clock, mapped to I2C5

Input

ISH_I2C_0_SCL_LS

J2.16

18

I2S-bit clock supplied by the module in master mode and serves as an input in slave mode.

Input

I2S_1_CLK_LS

J2.39

19

I2C port 1 data, mapped to I2C6

Bidirectional

ISH_I2C_1_SDA_LS

J2.23

20

MCLK for Master Mode operation of I2S audio

Input

CODEC_MCLK_LS

J2.43

21

I2C port 1 clock, mapped to I2C6

Input

ISH_I2C_1_SCL_LS

J2.21

22

UART port 1 transmit data, hardware strap with disable boot from eMMC functionality

J14 boot-strapping

UART_1_TXD_LS

J2.28

23

General purpose input/output 6

GPIO

ISH_GPIO_6_LS

J2.31

24

UART port 1 receive data.

Output

UART_1_RXD_LS

J2.26

25

General purpose input/output 5

GPIO

ISH_GPIO_5_LS

J2.38

26

Programmable pulse width modulator port 0

PWM Output

PWM_0_ LS

J2.1

27

General purpose input/output 4

GPIO

ISH_GPIO_4_LS

J2.29

28

Programmable pulse width modulator port 1

PWM Output

PWM_1_LS

J2.3

292

General purpose input/output 3, set as output by BIOS until reconfigured (see note 2 below)

GPIO

ISH_GPIO_3_LS

J2.34

30

Programmable pulse width modulator port 2

PWM Output

PWM_2_LS

J2.22

312

General purpose input/output 2, set as output by BIOS until reconfigured (see note 2 below)

GPIO

ISH_GPIO_2_LS

J2.32

32

Programmable pulse width modulator port 3

PWM Output

PWM_3_LS

J2.24

332

General purpose input/output 1, set as output by BIOS until reconfigured (see note 2 below)

GPIO

ISH_GPIO_1_LS

J2.27

34

System 1.8 VDC

+1.8V from Module

+VDD1

J2.36

352

General purpose input/output 0; set as output by BIOS until reconfigured (see note 2 below)

GPIO

ISH_GPIO_0_LS

J2.25

36

System Ground

Common Ground

GND

Multiple

37

System Ground

Common Ground

GND

Multiple

38

System Ground

Common Ground

GND

Multiple

39

System Ground

Common Ground

GND

Multiple

40

System 3.3 VDC

+3.3V from Module

+VDD3

J2.30

Notes:

  1. UART_0_TXD pin 7 is routed to a hardware-strapping pin on the Intel Joule module. Adding a pullup to this net or loading it with external circuitry such that it is not at a valid low input voltage at the rising edge of PMIC_PWRGOOD, on start-up will result in disabling aspects of the Converged Security Engine (CSE) which is responsible for retrieving and validating all firmware. See also Required Straps in the Design Guide section.
  2. During BIOS execution, the ISH_GPIO_0 through _3 signals are configured as outputs and change state to indicated BIOS progression. End users should take this into account in their design.

Breakout Connector J13

The table below provides the pin assignment, signal name, and description for the signals on the breakout connector J13. The default breakout usage refers to the vantage point of the expansion board. For example, the SPI_0_MISO signal originates in the breakout board and is delivered to the expansion board, therefore it is an input.

These signals are mapped by various operating systems in different ways. These mappings can change over time and with BIOS updates.

J13 Pin

Signal Description

Default
Breakout
Usage

Net Name at Breakout

Module
Pin

1

GND

Common Ground

GND

Multiple

2

5V

Voltage Rail

V5P0V

N / A

3

GND

Common Ground

GND

Multiple

4

5V

Voltage Rail

V5P0V

N / A

5

GND

Common Ground

GND

Multiple

6

3.3V

Voltage Rail

V3P3V

N / A

7

GND

Common Ground

GND

Multiple

8

3.3V

Voltage Rail

V3P3V

N / A

9

GND

Common Ground

GND

Multiple

10

1.8V

Voltage Rail

V1P8V

N / A

11

Reserved

Not used / Reserved

Reserved

J3.68

12

1.8V

Voltage Rail

V1P8V

N / A

13

Reserved

Not used / Reserved

Reserved

J3.64

14

GND

Common Ground

GND

Multiple

15

Reserved

Not used / Reserved

Reserved

J3.58

16

GPIO Pin 7

GPIO

FLASH_TORCH_LS

J3.75

17

Reserved

Not used / Reserved

Reserved

J3.56

18

GPIO Pin 8

GPIO

FLASH_RST_N_LS

J3.73

194

SPI port 0 slave select 0 (see note 4 below)

Output

SPI_0_FS0_LS

J3.77

20

GPIO Pin 9

GPIO

FLASH_TRIGGER_LS

J3.71

213

SPI port 0 chip select 1 (see note 3 below)

Input

SPI_0_FS1_LS_LS

J3.79

22

Microphone data for channels A and B

 -

AVS_M_DATA_1_LS

J3.66

23

SPI port 0 chip select 2

Input

SPI_0_FS2_LS

J3.53

24

Microphone clock for channel B (secondary microphone)

 -

AVS_M_CLK_B1_LS

J3.62

25

SPI port 0 clock

Input

SPI_0_CLK_LS

J3.59

26

Microphone clock for channel A (voice trigger microphone)

 -

AVS_M_CLK_A1_LS

J3.52

27

SPI port 0 transmit data

input

SPI_0_MOSI_LS

J3.57

28

UART port 0 receive data (Note: UART_0_TXD is on the J12 connector)

Output

UART_0_RXD_LS

J3.51

29

SPI port 0 receive data

Output

SPI_0_MISO_LS

J3.49

30

UART port 0 ready-to-send

UART Ready to send

UART_0_RTS_LS

J3.55

31

I2C port 1 data

Bidirectional

I2C_1_SDA_LS

J3.45

32

UART port 0 clear-to-send

UART - Clear to send

UART_0_CTS_LS

J3.47

33

I2C port 1 clock

Input

I2C_1_SCL_LS

J3.43

341

Although titled UART, function is configured as GPIO Pin 10 (see note 1 below)

GPIO

ISH_UART_0_TXD1_LS

J3.15

35

I2C port 1 data

Bidirectional

I2C_2_SDA_LS

J3.26

36

Although titled UART, function is configured as GPIO Pin 11

GPIO

ISH_UART_0_RXD_LS

J3.13

37

I2C port 2 clock

Input

I2C 2 SCL_LS

J3. 28

382

Although titled UART, function is configured as GPIO Pin 12 (see note 2 below)

GPIO

ISH_UART_0_RTS1_LS

J3.11

39

32.768 kHz RTC

Not used / Reserved

PMIC_SLPCLK_1_LS

J3.7

40

Although titled UART, function is configured as GPIO Pin 13

GPIO

ISH_UART_0_CTS_LS

J3.9

Notes:

  1. ISH_UART_0_TXD pin 34 is routed to a hardware-strapping pin on the Intel Joule module. Adding a pullup to this net or loading it with external circuitry such that it is not at a valid low input voltage at the rising edge of PMIC_PWRGOOD, on start-up will result in boot failure due to improper clock selection.
  2. ISH_UART_0_RTS pin 38 is routed to a hardware-strapping pin on the Intel Joule module. Adding a pulldown to this net or loading it with external circuitry such that it is not at a valid high input voltage at the rising edge of PMIC_PWRGOOD, on start-up will result in boot failure due to improper clock selection.
  3. SPI_0_FS1, pin 21, is routed to a hardware-strapping pin on the Intel Joule module. Adding a pullup to this net or loading it with external circuitry such that it is not at a valid low input voltage at the rising edge of PMIC_PWRGOOD, on start-up will result in boot failure due to boot halt being enabled.
  4. SPI_0_FS0 pin 19 is routed to a hardware-strapping pin on the Intel Joule module. Adding a pullup to this net or loading it with external circuitry such taht it is not at a valid low input voltage at the rising edge of PMIC_PWRGOOD, on start-up will result in boot failure.

 

See also Required Straps in the Design Guide section.

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