The Imaging Processing Unit (IPU) consists of the Processing Subsystem (PS) and the Input Subsystem (IS). The Processing Subsystem is an advanced Image Signal processor (ISP). The Input Subsystem contains the MIPI CSI2 controllers. The IPU interfaces with the CMOS image sensors in the camera module through the IS and processes still and video frames in the PS.
Number of Cameras Supported
- The IPU can support a maximum of four cameras
- Typical expected usage is one primary camera and one secondary camera
- Allocating four cameras between world and user-facing views is ultimately at the designer’s discretion
- All cameras can be active at the same time
- The IS saves streams to memory for off line processing and for one primary camera
- On-the-fly processing is also supported
Still Image and Video Resolution
|Primary Camera Still Image||The IPU hardware is capable of supporting sensor resolutions up to 13 Megapixel (MP)|
|Secondary Camera Still Image||Maximum secondary camera still image resolution is 5 Megapixel (MP)|
|Primary Camera Video||Maximum primary camera video resolution is 2160p30.|
|Secondary Camera Video||Maximum secondary camera video resolution is 1080p60.|
The IPU has built-in DMA engines that support reading and writing streams from/to DRAM. These include storing the raw frames in memory as it comes from the sensors, reading previous frames for processing, and writing back the processed frame to memory. The IPU processes images block by block. The blocks may be lines or tiles depending on the processing model being used. While the PS processes the current block, the DMA engines concurrently store the previously processed block to memory and fetch the data needed for processing the next block. These DMA operations must complete before processing for the next block starts.
The PS uses a clock derived from a local PLL, with Dynamic Voltage and Frequency Scaling (DVFS) support. This clock can be dynamically changed at runtime to allow the performance and power profile of the PS to be changed in response to changing usage models and loads.
Dynamic Frequency Scaling
Driver software can request the frequency of the PS clock to be changed via updating the PS clock control register. The PS supports only asynchronous frequency changes, where the requested clock is stopped until the PLL generates the new requested frequency. During the time the clock is stopped, logic will remain stalled in the PS. The IS will continue to run, as it is not on the PS clock, and any incoming pixel streams will be getting buffered in the IS pixel buffer. The IS clock is not affected by PS clock scaling.
The IS can provide a clock to the sensor (or other imaging components) to reduce system BOM costs. There are three clock outputs, each of which may be independently enabled using OSC_CLK_OUTn_enable bits in the SENSOR_CLK_CTL register.
See also: Camera Introduction and the topics that follow in the Programmers Guide for more information about using the imaging capabilities.