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Intel Cluster Ready FAQ: Hardware vendors, system integrators, platform suppliers
By Werner Krotz-vogel (Intel)Posted 03/23/20150
Q: Why should we join the Intel® Cluster Ready program? A: By offering certified Intel Cluster Ready systems and certified components, you can give customers greater confidence in deploying and running HPC systems. Participating in the program will help you drive HPC adoption, expand your custom...
Intel Cluster Ready FAQ: Customer benefits
By Werner Krotz-vogel (Intel)Posted 03/23/20150
Q: Why should we select a certified Intel Cluster Ready system and registered Intel Cluster Ready applications?A: Choosing certified systems and registered applications gives you the confidence that your cluster will work as it should, right away, so you can boost productivity and start solving n...
Dynamic allocator replacement on OS X* with Intel® TBB
By Kirill Rogozhin (Intel)Posted 03/23/20150
The Intel® Threading Building Blocks (Intel® TBB) library provides an alternative way to dynamically allocate memory - Intel TBB scalable allocator (tbbmalloc). Its purpose is to provide better performance and scalability for memory allocation/deallocation operations in multithreaded applications...
Courseware Algorithmic Strategies
By adminPosted 02/27/20150
Brute-force algorithms Greedy algorithms Divide-and-conquer Backtracking Branch-and-bound Heuristics Pattern matching and string/text algorithms Numerical approximation algorithms     Parallel Solution to Cat-and-Mouse strategy game problem (Vyukov)     Material Type: Codi...
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VTune™ Amplifier XE 2015 Update 2 supports for driverless hardware event-based sampling with call stack info
By Peter Wang (Intel) Posted on 03/15/15 1
In general, vtune drivers will be built and loaded to the Linux* system automatically during installing VTune™ Amplifier XE product, then hardware PMU event-based sampling can work.  However sometime, vtune drivers were built/loadeded unsuccessfully, because of one of below reason: 1.    There ...
Intel® Xeon Phi™ Coprocessor Developer Training Coming to a City Near You in 2015
By Mike Pearce (Intel) Posted on 03/04/15 0
Intel is offering an updated and expanded series of software developer trainings in parallel programming using the Intel® Xeon Phi™ coprocessor.
Advanced Computer Concepts For The (Not So) Common Chef: Introduction
By Taylor Kidd (Intel) Posted on 02/20/15 2
While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the Intel® Xeon Phi™ ⅹ100 and ⅹ200 architectures. The first topic that came up was hyper-threading, and more specifically, the coprocessor’s version of hyper-thr...
Introduction to OpenMP* on YouTube
By Mike Pearce (Intel) Posted on 12/03/14 0
Tim Mattson (Intel), has authored an extensive series of excellent videos as in introduction to OpenMP*. Not only does he walk through a series of programming exercises in C, he also starts with a background introduction on parallel programming. Check out the series:
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speedup problem using openMP in intel fortran
By bohluly2
Dear all, I have developed  a program and unfortunately I have speedup problem in it. My program is so big so I have tried to write a sample similar to my program, fortunately this simple program has a same problem with my program.  I need other experiences and your help if it is possible. Thanks, I am using VS2010 and Intel FORTRAN XE 2011 Program:     TYPE var         REAL(8),POINTER :: A, B, C      END TYPE var      REAL(8),POINTER :: A(:), B(:), C(:)      TYPE(var),POINTER  :: vars(:)        TYPE(var),POINTER :: varOMP            REAL*8  t1,t2 ,ai,bi,ci,di,ei,fi        INTEGER(4) c1,c2      INTEGER N, CHUNKSIZE, I, id, f , l      PARAMETER (N=200)      PARAMETER (CHUNKSIZE=10)            Allocate (A(N), B(N), C(N),vars(N)) !     initializations         DO I = 1, N          A(N)      =   I * 1.0          B(N)      =   A(N)          vars(I)%A =>  A(N)          vars(I)%B =>  B(N)          vars(I)%C =>  C(N)          vars(I)%A = 0.51          vars(I)%B...
How can I verify license key?
By Aleksandr S.1
I have bought few Xeon Phi units. The reseller provided with keys for Intel Parallel Studio. I think they are 6 months demo. However I'd like to know for sure. Is there a way I can check the terms of these keys without activating them, directly with Intel?
Doubts before buy Intel Studio
By Marcelo C.2
Hi All   I have some doubts regarding the Intel software studio for parallel arch and the Brazilian seller is not able to answer. I need to solve these doubts before buy the Studio for my company. Can somebody help me? 1- Currently we are using OpenMPI. Which advantages Intel MPI provides over OpenMPI? 2- OpenMPI error handling is not good. The MPI Lib from Intel is better for error handling and recovering? For example, if one rank in my mpi comm world dies how can I handle this using Intel lib? 3- Currently we use GCC. Intel compiler is better? We are running in a cluster with several nodes, with MPI doing the communication between the nodes.  Any other recommendations? We host our application at Amazon.  Thank you all in advance!  
Openmp task and parallel construct
By Patrice l.1
Hi, I am trying to understand the behavior of the Openmp implementation when a parallel do is enclosed in a task. When using nested  the parallel do uses multiple threads. The first question is is that possible to restrict the number of threads to the original thread pool (hardware thread), so that they work on the parallel construct has they become available after completing other task ? (see code below) From reading the forum, i suspect the answer will be no, then what is the best way to combine task and parallel do , inside a task and outside a task. Is it worth it to close the master or single region to do a parallel one, and reopen it right after ? Last question, is there any  becnhmark of using task for a loop instead of a classic parallel do , in both case, fixed work load, and variable work load for each iteration ?   Thanks program omptest use omp_lib implicit none integer :: i !$omp parallel !$omp master print *,'omp get max threads',omp_get_max_thr...
Draining store buffer on other core
By Boris D.10
Hello, I've a weird question: As I understand, mfence instruction causes draining of the store-buffer on the same core on which it was executed. Is there some way for thread on core A, to cause draining of the store-buffer of core B, without running on core B? Maybe some dirty tricks like simulating IO or exception interrupts?   Thanks!
TBB error : atomic is undefined
By Aleksandr S.1
I got a C++ code in VS2013 using Intel Compiler XE 15. I write #include "tbb/atomic.h" ...atomic<int> x; I get identifier 'atomic' is undefined. what did I do wrong?
Thread heap allocation in NUMA architecture lead to decrease performance
By hamed i.4
hi i have server that has 80 logical core (model:dl580g7) .I'm running a single thread per core. each thread doing mkl fft , convolution and many Allocation and DeAllocation from heap with malloc. i previously have server with 16 logical core and there was not a problem and each thread work on its core with 100% cpu usage. when i moved my application from that 16 core server to this 80 core server with numa architecture , after create first thread , that thread works on 100%(kernel time 0%) and With the addition of each thread, performance of other thread decrease so that finally when i have 80 thread cpu usage downgrade to 40% (39% kernel time). because kernel time is increased ,I think the reason for this event is heap sequential mechansim and heap lock. Because of the increasing demand for memory allocation,increased waiting time for each request. i use createheap() on each thread  to eliminate wait for unlock heap memory. but heapalloc can alloc memory up to 512KB. that Insuffic...
A new algorithm of a scalable distributed sequential lock
By aminer100
Scalable distributed sequential lock Scalable Distributed Sequential lock     Scalable Distributed Sequential lock version 1.11 Author: Amien Moulay Ramdane.  Description: This scalable distributed sequential lock was invented by Amine Moulay Ramdane, and it combines the characteristics of a distributed reader-writer lock with the characteristics of a sequential lock , so it is a clever hybrid reader-writer lock that is more powerful than the the Dmitry Vyukov's distributed reader-writer mutex , cause the Dmitry  Vyukov's distributed reader-writer lock will become slower and slower on the writer side with more and more cores because it transfers too many cache-lines between cores on the writer side, so my invention that is my scalable distributed sequential lock has eliminated this weakness of the Dmitry Vyukov's distributed reader-writer mutex,  so that the writers throughput has become faster and very fast, and my scalable distri...
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