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Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
By Indraneil Gokhale (Intel)Posted 09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
Intel® IPP - Threading / OpenMP* FAQ
By Naveen GvPosted 04/08/20157
This page contains common questions and answers on multi-threading in the Intel IPP.
Threading Intel® Integrated Performance Primitives Image Resize with Intel® Threading Building Blocks
By Jeffrey Mcallister (Intel)Posted 04/08/20150
Threading Intel® IPP Image Resize with Intel® TBB.pdf (157.18 KB) :Download Now   Introduction The Intel® Integrated Performance Primitives (Intel® IPP) library provides a wide variety of vectorized signal and image processing functions. Intel® Threading Building Blocks (Intel® TBB) adds simpl...
License changes in Intel® Parallel Studio XE 2016 Beta
By Gergana Slavova (Intel)Posted 03/30/20150
This Beta release of the Intel® Parallel Studio XE 2016 introduces a major change to the 'Named-user' licensing scheme (provided as default for the 2016 Beta licenses).  Read below for more details on this new functionality as well as a list of special exceptions.  Following a thorough Beta testi...
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What exactly is a P-state? (Pt. 1)
By Taylor Kidd (Intel) Posted on 04/06/15 6
    A P-state is a voltage and frequency operating point       What is a P-state? When someone refers to a P-state, generally only the frequency is talked about. For example, on my Intel® Core™ processor, P0 is 2.3 GHz, and P1 is 980 MHz. In truth, a P-state is both a frequency and volt...
C-states and P-states are very different
By Taylor Kidd (Intel) Posted on 04/06/15 13
C-states are idle states and P-states are operational states. This difference, though obvious once you know, can be initially confusing. With the exception of C0, where the CPU is active and busy doing something, a C-state is an idle state. Since an idle CPU isn't doing anything (i.e. any usefu...
Videos - Parallel Programming with Intel Xeon Phi Coprocessors
By Mike Pearce (Intel) Posted on 03/30/15 0
Here is a list of recently published videos from Colfax International on Intel(R) Xeon Phi(TM) Coprocessors. Software Tools for Intel Xeon Co-processors In this video we will discuss software tools needed and recommended for developing applications for Intel Xeon Phi coprocessors. We wi...
Videos - Parallel Programming and Optimization with Intel Xeon Phi Coprocessors
By Mike Pearce (Intel) Posted on 03/30/15 0
Here is a set of introductory videos from Colfax International on Parallel Programming and Optimization with Intel(R) Xeon Phi(TM) Coprocessors. Episode 2.1 - Purpose of the MIC architecture In this video episode we will introduce Intel Xeon Phi coprocessors based on the Intel Many Inte...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
error when compile parsec with icc.
By sun l.0
error when compile http://parsec.cs.princeton.edu/parsec3-doc.htm with icc. What's "/opt/intel/cc/latest"? it doesn't exist on my machine. should i make a cc fold? ---------- [root@amax parsec-3.0]# cd /opt/intel [root@amax intel]# ls bin                     composerxe  ism       mic     cnc                     impi        lib       mkl     include     licenses  mpi-rt     ipp         man       tbb [root@amax parsec-3.0]# whereis icc icc: /opt/intel/bin/icc [root@amax parsec-3.0]# whereis cc cc: /usr/bin/cc --------------  some config of icc.bldconf # CC_HOME is the installation root of the C compiler   export CC_HOME="/opt/intel/cc/latest"   #  export CC_HOME="/opt/intel/bin/" when i changed CC_HOME to "/opt/intel/bin/", still error     ----------- [root@amax parsec-3.0]# parsecmgmt -a build -c icc [PARSEC] Packages to build:  blackscholes bodytrack facesim ferret freqmine raytrace swaptions fluidanimate vips x264 canneal dedup streamcluster [PARSEC] [========== Build...
Parallel Image Processing in OpenMP - Image Blocks
By Royi5
Hello, I'm doing my first steps in the OpenMP world. I have an image I want to apply a filter on. Since the image is large I wanted to break it into non overlapping parts and apply the filter on each independently in parallel. Namely, I'm creating 4 images I want to have different threads. I'm using Intel IPP for the handling of the images and the function to apply on each sub image. I described the code here: http://stackoverflow.com/questions/29319226/parallel-image-processing-in... The problem is I tried both sections and parallel for and got only 20% improvement. What am I doing wrong? How can I tell each "Worker" that though data is taken from the same array, it is safe to read (Data won't change) and write (Each worker has exclusive approach to its part of the result image). Thank You.
COPROCESSADOR PHI AND JAVA
By Rafael R.2
Hi, In our university bought a machine with CO-PROCESSOR PHI. The description in the site: https://software.intel.com/en-us/articles/intelr-xeon-phitm-coprocessor-... It is reported that there is no support JAVA yet. The answer is 2013 and we are already in 2015. Is there a Java option for coding? Tks Rafael
Intel® Xeon Phi™ Coprocessor Developer Training Coming to a City Near You in 2015
By Mike Pearce (Intel)0
https://software.intel.com/en-us/blogs/2015/03/04/intel-xeon-phi-coprocessor-developer-training-coming-to-a-city-near-you-in-2015
Mixing kernel space and userspace in a new kernel.
By Jog L.0
Hello, I was thinking of creating an open source kernel (with block already written in the linux kernel obviously). Now I would like to hear from experts what are the dangers to run in ring0 if no users and no external connections are done. We are in a situation in which the processor is isolated from the whole world. No one can mess with it. all the processes running on top of it have to register and are created and compiled by root using a specific memory range. No process can be launched without the acceptation of root. No human accesses it. The code running inside is reviewed and we have facilities to be sure no other memory range than the one we expect each process to use can be used. That is for the -restrictive- context. Now, could we imagine it be possible for such a kernel to exist or are there some limitations that I don't predict ? The kernel is to be massively specialized, hence the "almost starting from scratch". Thanks for your insights, Jog
linking with two versions of mkl (multi threaded and single threaded) in one application
By Michal K.3
Hi, Is it possible to use both the single threaded version of mkl library and the multi threaded version of mkl in one application? I need the single threaded version to use with PLASMA library, yet at some other part of my code, I need use mkl PARDISO, for which I need the multi threaded version. Any help will be greatly appreciated. Cheers Michal  
PCIe 3.0 reference clock jitter tool
By Sonal C.0
Where can I access the Intel PCIe clock jitter tool
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