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Just published! Intel® Xeon Phi™ Coprocessor High Performance Programming 
Learn the essentials of programming for this new architecture and new products. New!
Intel® System Studio
The Intel® System Studio is a comprehensive integrated software development tool suite solution that can Accelerate Time to Market, Strengthen System Reliability & Boost Power Efficiency and Performance. New!
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Introduction to High Performance Application Development for Intel® Xeon & Intel® Xeon Phi™ Coprocessors.
Structured Parallel Programming
Authors Michael McCool, Arch D. Robison, and James Reinders uses an approach based on structured patterns which should make the subject accessible to every software developer.

Deliver your best application performance for your customers through parallel programming with the help of Intel’s innovative resources.

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Intel® Parallel Studio XE ›

Bringing simplified, end-to-end parallelism to Microsoft Visual Studio* C/C++ developers, Intel® Parallel Studio XE provides advanced tools to optimize client applications for multi-core and manycore.

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Parallel Programming Talk Radio - Aug 13th at 8:00AM PST - Our next guest it Interactive Supercomputing
By aaron-tersteeg (Intel)Posted 08/11/20080
The next show is scheduled for August 13th at 8:00AM PST. Clay and I will be talking with David Rich, Vice President of Marketing at Interactive Supercomputing. Interactive Supercomputing is helping researchers and engineers build, optimize and run parallel programs using MATLAB* and Python for ...
Characterization of SPECpower_ssj2008** benchmark
By Anil Kumar (Intel)Posted 08/06/20080
Abstract SPEC** recently released SPECpower_ssj2008, the first industry benchmark to measure performance and power of volume server class computers using graduated load levels. In this paper, we present a brief overview and an initial characterization of SPECpower_ssj2008 by measuring the utili...
The Intel Developer Forum is August 19 - 21, 2008 | San Francisco | Moscone Center West
By aaron-tersteeg (Intel)Posted 08/05/20080
If your in town and interested in connecting please drop me a line and we'll plan to meet up. My email is aaron d0t c d0t tersteeg at intel d0t com.
Critical Analysis of the Need For Parallelizing Network Stacks
By Annie Foong (Intel)Posted 07/30/20081
by Annie Foong, Network Research Scientist Erik J. Johnson, Network Software Engineer Introduction In the new era of “parallelize or paralyze”, the rush to thread software is on. In this article, we make a case that it pays to critically analyze which parts of our software to parallelize first....
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Good-bye, Tech-Ed'08 and see you next year!
By mike-huelskoetter Posted on 11/18/08 0
So, Microsoft Tech-Ed EMEA Developers 2008 is history and we had a lot of fun, great technical chats with people, crowded tech sessions and deep interest in Intel programming tools. So we counted more than 200 people at Ralph‘s and Edmund‘s tech sessions, several hundred guys at the Intel stand a...
Meet the new stars in the Intel Software Network Hall of Fame!
By gunjan-rawal (Intel) Posted on 11/18/08 2
In addition to the Black Belt, Brown Belt and Green Belt Software Developer titles, I am going be updating the Hall of Fame Page periodically with the objective of recognizing members of our communities who go above and beyond, help other members and strengthen our communities through their high-...
Correctness and Threading
By David Mackay (Intel) Posted on 11/17/08 1
We have often stated the three main points of parallelism are: Correctness, Scalability, and Maintainability.    We are working to provide better tools to improve all three aspects of software development.  The other month I wrote about Intel Threading Building Blocks which helps provide an abstr...
OpenSolaris and Xeon Processors #10 - Turbo Mode
By David Stewart (Intel) Posted on 11/14/08 4
Here's the latest video in the series I am doing on OpenSolaris and Intel Xeon processors. This is about an exciting feature called "Turbo Mode" we have available in our new Intel Core Microarchitecture (aka "Nehalem"). I also give props to the community work on the "Power Aware Dispatcher" which...
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Poor threading performance on Intel Xeon E5-2680 v2
By Pascal10
Hello I am running a visualization program (visualizing a large dataset) where I can either use MPI or pthreads. When I run it on my desktop which has an Intel i7-2600K (4 cores, 8 threads), I get better performance using pThreads (I'm using a lot of threads, e.g 32) compared to using MPI which is normal (I guess). But when I run the same code on one node (which is part of a cluster) which has Intels Xeon E5-2680 v2 (10 cores, 20 threads), the performance I get using pthreads is worse than MPI; about 70s while using MPI compared to 180s using pthreads. Even worse, the performance on the Intel Xeon E5-2680 v2 is lower than on that of the Intel i7-2600K, it's around 100s on the 2600k but 180 on the  E5-2680 (same number of threads on both). I check using the top command and all the cores are active when I run the program.   So my question is why is that happening? Is there some other way I should be compiling the code on the E5-2680? Is there some variables I should set like KMP_AFFIN...
HTM/STM and Scheduling
By Simone A.1
Hi, I have a question about Hardware and Software Transactional Memory. Given the types of versioning (eager and lazy) and conflict detection (optimistic and pessimistic) and let's say that 2 or more threads are performing a transaction that write/read the same memory location. The scheduling of the threads could affect the ability of detect a conflict? Which combination of versioning and conflict detection would be better to always catch the conflicts? Hope my question is clear. Thanks. Best Regards, Simone
Locking CPU cache lines for a thread ( L1)
By Younis A.14
Hi I'm working on securing access to L1 cache by locking it line by line. Is there any way to do it? For example, two threads accessing the L1 and L1 lines are locked for a certain time to each thread accessed them. Regards, Younis
Responsive OpenMP Theads in Hybrid Parallel Environment
By Don K.1
I have a Fortran code that runs both MPI and OpenMP.  I have done some profiling of the code on an 8 core windows laptop varying the number of mpi  tasks vs. openmp threads and have some understanding of where some performance bottlenecks for each parallel method might surface.  The problem I am having is when I port over to a Linux cluster with several 8-core nodes.  Specifically, my openmp thread parallelism performance is very poor.  Running 8 mpi tasks per node is significantly faster than 8 openmp threads per node (1 mpi task), but even 2 omp threads + 4 mpi tasks runs was running very slowly, more so than I could solely attribute to a thread starvation issue.  I saw a few related posts in this area and am hoping for further insight and recommendations in to this issue.  What I have tried so far ... 1.  setenv OMP_WAIT_POLICY active      ## seems to make sense 2.  setenv KMP_BLOCKTIME 1          ## this is counter to what I have read but when I set this to a large number (2500...
Optimizing cilk with ternary conditional
By Fabio G.3
What is the best way to optimize the cycle cilk_for(i=0;i<n;i++){ x[i]=x[i]<0?0:x[i]; }or somethings like that? Thanks, Fabio
have asked them to
By Robert P.0
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Optimizing reduce_by_key implementation using TBB
By Shruti R.0
Hello Everyone, I'm quite new to TBB & have been trying to optimize reduce_by_key implementation using TBB constructs. However serial STL code is always outperforming the TBB code! It would be helpful if I'm given an idea about how reduce_by_key can be improvised using tbb::parallel_scan. Any help at the earliest would be much appreciated. Thanks.
reading a shared variable
By VIKRANT G.4
hello everyone I am relatively new to parallel programming and have the following doubt:- is reading a shared variable(that is not modified by any thread) without using locks a good practice thanks for the help in advance  
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