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Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
By Indraneil Gokhale (Intel)Posted 09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
Improve Server Application Performance with Intel® Advanced Vector Extensions 2
By Thai Le (Intel)Posted 04/30/20150
The Intel® Xeon® processor E7 v3 family now includes an instruction set called Intel® Advanced Vector Extensions 2 (Intel® AVX2), which can potentially improve application performance related to high performance computing, databases, and video processing. To validate this statement, I performed a...
Accelerating Financial Applications on Intel® architecture
By George Raskulinec (Intel)Posted 04/29/20150
Download PDF Accelerating Financial Applications on Intel Architecture [PDF 575.55KB] Download File QuantLib_optimized_for_IA.tar.gz [TAR 522.48KB] Abstract:   A paper titled Accelerating Financial Applications on the GPU compared GPU vs. CPU performance using four QuantLib library financial ...
Introducing Batch GEMM Operations
By Zhang Z (Intel)Posted 04/28/20150
The general matrix-matrix multiplication (GEMM) is a fundamental operation in most scientific, engineering, and data applications. There is an everlasting desire to make this operation run faster. Optimized numerical libraries like Intel® Math Kernel Library (Intel® MKL) typically offer parallel ...
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Videos - Parallel Programming with Intel Xeon Phi Coprocessors
By Mike Pearce (Intel) Posted on 03/30/15 0
Here is a list of recently published videos from Colfax International on Intel(R) Xeon Phi(TM) Coprocessors. Software Tools for Intel Xeon Co-processors In this video we will discuss software tools needed and recommended for developing applications for Intel Xeon Phi coprocessors. We wi...
Videos - Parallel Programming and Optimization with Intel Xeon Phi Coprocessors
By Mike Pearce (Intel) Posted on 03/30/15 0
Here is a set of introductory videos from Colfax International on Parallel Programming and Optimization with Intel(R) Xeon Phi(TM) Coprocessors. Episode 2.1 - Purpose of the MIC architecture In this video episode we will introduce Intel Xeon Phi coprocessors based on the Intel Many Inte...
Advanced Computer Concepts for The (Not So) Common Chef: First Some Terminology Part 2
By Taylor Kidd (Intel) Posted on 03/25/15 0
OF COURSE, I KNOW WHAT A THREAD IS….DON’T I? Now that we know what a core is, let’s dive into another source of confusion. This section gets a little deeper into techno babble than I wanted for this series of blogs. If you are so inclined, my gourmet readers, you can either skip or read on. I b...
Advanced Computer Concepts For The (Not So) Common Chef: Terminology Pt 1
By Taylor Kidd (Intel) Posted on 03/24/15 0
Before we start, I will use the next two blogs to clear up some terminology. If you are familiar with these concepts, I give you permission to jump to the next section.  I suggest any software readers still check out the other blog about threads. There is a lot of confusion, even among us softwar...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
I have a problem with igzip
By gq L.0
Hi! I am studying about compression algorithm and software. I have question about igzip. I download igzip library in intel homepage. But I don`t know how to make wrapper. Can you send me 'example of wrapper' or 'example code' or 'manual'? I read homepage and saw a simple application. I don`t know how to input target file for compression and to output compression file and how to decompression? Do I make code about 'fast_lz and init_stream' function by myself? Plz help me. thank you
PCM reporting lower than expected memory read counts
By Patrick L.2
I have a piece of code on which I'm running PCM (Performance Counter Monitor). It is essentially the following: uint64_t *a,*b; a = new uint64_t[LEN]; b = new uint64_t[LEN]; for( int i=0;i<LEN;i++ ) a[i] = b[i];With LEN set to 402,653,184 (384 Mi), PCM is reporting 0.72 GB under READ and 6.30 GB under WRITE. Given that each array is 3 GiB, I would expect that both arrays would be read (since processor uses write-allocate), giving a READ of about 6 GiB. I would expect array "a" to be written back, giving a write count of 3 GiB. Does anyone know why the read count is so low, and the write count is higher than expected? Processor is Intel Core i7 940 (Nehalem). Any help is appreciated. Patrick
igzip 'make' problem
By gq L.1
Hi   I download igzip_042.zip and modify YASM path of Makefile   but it doesn`t make .exe file   I don`t know igzip execution sequence   If you have document about igzip, plz share it.   Thank you
igzip 'make' problem
By gq L.0
Hi I download igzip_042.zip and modify YASM path of Makefile but it don`t make .exe file I don`t know igzip execution sequence If you have document about igzip, plz share it. Thank you
error when compile parsec with icc.
By sun l.0
error when compile http://parsec.cs.princeton.edu/parsec3-doc.htm with icc. What's "/opt/intel/cc/latest"? it doesn't exist on my machine. should i make a cc fold? ---------- [root@amax parsec-3.0]# cd /opt/intel [root@amax intel]# ls bin                     composerxe  ism       mic     cnc                     impi        lib       mkl     include     licenses  mpi-rt     ipp         man       tbb [root@amax parsec-3.0]# whereis icc icc: /opt/intel/bin/icc [root@amax parsec-3.0]# whereis cc cc: /usr/bin/cc --------------  some config of icc.bldconf # CC_HOME is the installation root of the C compiler   export CC_HOME="/opt/intel/cc/latest"   #  export CC_HOME="/opt/intel/bin/" when i changed CC_HOME to "/opt/intel/bin/", still error     ----------- [root@amax parsec-3.0]# parsecmgmt -a build -c icc [PARSEC] Packages to build:  blackscholes bodytrack facesim ferret freqmine raytrace swaptions fluidanimate vips x264 canneal dedup streamcluster [PARSEC] [========== Build...
Parallel Image Processing in OpenMP - Image Blocks
By Royi5
Hello, I'm doing my first steps in the OpenMP world. I have an image I want to apply a filter on. Since the image is large I wanted to break it into non overlapping parts and apply the filter on each independently in parallel. Namely, I'm creating 4 images I want to have different threads. I'm using Intel IPP for the handling of the images and the function to apply on each sub image. I described the code here: http://stackoverflow.com/questions/29319226/parallel-image-processing-in... The problem is I tried both sections and parallel for and got only 20% improvement. What am I doing wrong? How can I tell each "Worker" that though data is taken from the same array, it is safe to read (Data won't change) and write (Each worker has exclusive approach to its part of the result image). Thank You.
COPROCESSADOR PHI AND JAVA
By Rafael R.2
Hi, In our university bought a machine with CO-PROCESSOR PHI. The description in the site: https://software.intel.com/en-us/articles/intelr-xeon-phitm-coprocessor-... It is reported that there is no support JAVA yet. The answer is 2013 and we are already in 2015. Is there a Java option for coding? Tks Rafael
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