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Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
By Indraneil Gokhale (Intel)Posted 09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
Courseware Algorithmic Strategies
By adminPosted 02/27/20150
Brute-force algorithms Greedy algorithms Divide-and-conquer Backtracking Branch-and-bound Heuristics Pattern matching and string/text algorithms Numerical approximation algorithms     Parallel Solution to Cat-and-Mouse strategy game problem (Vyukov)     Material Type: Codi...
Courseware - Software Processes
By adminPosted 02/27/20150
Software life-cycle and process models Software process capability maturity models Approaches to process improvement Process assessment models Software process measurements     CSE445/598 Project on Multithreading and Multi-Core Processing (ASU)     Material Type: Problem set...
Courseware - Data Structures
By adminPosted 02/27/20150
Representation of numeric data Range, precision, and rounding errors Arrays Representation of character data Strings and string processing Runtime storage management Pointers and references Linked structures Implementation strategies for stacks, queues, and hash tables Implementation str...
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By Taylor Kidd (Intel) Posted on 02/20/15 2
  TITLE: INTRODUCTION ADVANCED COMPUTER CONCEPTS FOR THE (NOT SO) COMMON CHEF While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the Intel® Xeon Phi™ ⅹ100 and ⅹ200 architectures. The first topic that came up ...
Introduction to OpenMP* on YouTube
By Mike Pearce (Intel) Posted on 12/03/14 0
Tim Mattson (Intel), has authored an extensive series of excellent videos as in introduction to OpenMP*. Not only does he walk through a series of programming exercises in C, he also starts with a background introduction on parallel programming. Check out the series:
Benefits of Intel(R) Cache Monitoring Technology in the Intel(R) Xeon(TM) Processor E5 v3 Family
By Khang Nguyen (Intel) Posted on 09/08/14 0
Introduction The number of cores is increasing with the introduction of new processors.  As more cores are added, the number of diverse workloads that potentially can run simultaneously is also increasing.  Workloads can be single-threaded or multi-threaded applications and they can run in nativ...
Web Resources about Intel® Transactional Synchronization Extensions
By Roman Dementiev (Intel) Posted on 07/28/14 3
Short URL for this page: In this blog I list useful technical resources related to Intel® Transactional Synchronization Extensions (Intel TSX). I will try to keep the list up-to-date as new material becomes available (subscribe to this page below to get update notifica...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Mixing kernel space and userspace in a new kernel.
By Jog L.0
Hello, I was thinking of creating an open source kernel (with block already written in the linux kernel obviously). Now I would like to hear from experts what are the dangers to run in ring0 if no users and no external connections are done. We are in a situation in which the processor is isolated from the whole world. No one can mess with it. all the processes running on top of it have to register and are created and compiled by root using a specific memory range. No process can be launched without the acceptation of root. No human accesses it. The code running inside is reviewed and we have facilities to be sure no other memory range than the one we expect each process to use can be used. That is for the -restrictive- context. Now, could we imagine it be possible for such a kernel to exist or are there some limitations that I don't predict ? The kernel is to be massively specialized, hence the "almost starting from scratch". Thanks for your insights, Jog
linking with two versions of mkl (multi threaded and single threaded) in one application
By Michal K.3
Hi, Is it possible to use both the single threaded version of mkl library and the multi threaded version of mkl in one application? I need the single threaded version to use with PLASMA library, yet at some other part of my code, I need use mkl PARDISO, for which I need the multi threaded version. Any help will be greatly appreciated. Cheers Michal  
PCIe 3.0 reference clock jitter tool
By Sonal C.0
Where can I access the Intel PCIe clock jitter tool
Memory to CPU (mov) bandwidth limitations
By albus d.3
(sorry for weak english I am not native english, Not sure if right forum, first time here - This is general about some hardware limits i do not understand technical reason and I would very like to know) We have now parallelised SIMD arithmetic (like 8 float mulls or divisions in one step) theoretical (but also nearly practical) arithmetical bandwidth per core is thus like 4GHz * 8 floats = about 30 GFLOPS per core or something like that But we still AFAIK have quite low RAM to CPU bandwidth at the level of read or write of 1 or 2 int of float per nanosecond, such ram-2-cpu bandwidth when i am testing it is like only 2 GLOP per second per core or something like that; (both those values are rough but this difference seem to be physical truth at least from my experience) I mean arithmetic can be paralelised (like 8-vectorised) but load/store movs are not - thus SIMD paralistation has obly a fraction of its potential power This is extremally crusial to increase this memory bandwith (muc...
speedup problem using openMP in intel fortran
By bohluly2
Dear all, I have developed  a program and unfortunately I have speedup problem in it. My program is so big so I have tried to write a sample similar to my program, fortunately this simple program has a same problem with my program.  I need other experiences and your help if it is possible. Thanks, I am using VS2010 and Intel FORTRAN XE 2011 Program:     TYPE var         REAL(8),POINTER :: A, B, C      END TYPE var      REAL(8),POINTER :: A(:), B(:), C(:)      TYPE(var),POINTER  :: vars(:)        TYPE(var),POINTER :: varOMP            REAL*8  t1,t2 ,ai,bi,ci,di,ei,fi        INTEGER(4) c1,c2      INTEGER N, CHUNKSIZE, I, id, f , l      PARAMETER (N=200)      PARAMETER (CHUNKSIZE=10)            Allocate (A(N), B(N), C(N),vars(N)) !     initializations         DO I = 1, N          A(N)      =   I * 1.0          B(N)      =   A(N)          vars(I)%A =>  A(N)          vars(I)%B =>  B(N)          vars(I)%C =>  C(N)          vars(I)%A = 0.51          vars(I)%B...
How can I verify license key?
By Aleksandr S.1
I have bought few Xeon Phi units. The reseller provided with keys for Intel Parallel Studio. I think they are 6 months demo. However I'd like to know for sure. Is there a way I can check the terms of these keys without activating them, directly with Intel?
Doubts before buy Intel Studio
By Marcelo C.2
Hi All   I have some doubts regarding the Intel software studio for parallel arch and the Brazilian seller is not able to answer. I need to solve these doubts before buy the Studio for my company. Can somebody help me? 1- Currently we are using OpenMPI. Which advantages Intel MPI provides over OpenMPI? 2- OpenMPI error handling is not good. The MPI Lib from Intel is better for error handling and recovering? For example, if one rank in my mpi comm world dies how can I handle this using Intel lib? 3- Currently we use GCC. Intel compiler is better? We are running in a cluster with several nodes, with MPI doing the communication between the nodes.  Any other recommendations? We host our application at Amazon.  Thank you all in advance!  
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