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Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
By Indraneil Gokhale (Intel)Posted 09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
GROMACS recipe for symmetric Intel® MPI using PME workloads
By Heinrich Bockhorst (Intel)Posted 05/27/20150
Objectives This package (scripts with instructions) delivers a build and run environment for symmetric MPI runs. This file is actually the README of the package. Symmetric stands for employing a Xeon® executable and a Xeon Phi™ executable both running together exchanging MPI messages and collect...
Building and Running 3D-FFT Code that Leverages MPI-3 Non-Blocking Collectives with the Intel® Parallel Studio XE Cluster Edition
By Mark Lubin (Intel)Posted 05/26/20150
Purpose This application note assists developers with using Intel® Software Development Tools with the 3D-FFT MPI-3 based code sample from the Scalable Parallel Computing Lab (SPCL), ETH Zurich. Introduction The original 3D-FFT code based on the prototype library libNBC was developed to help i...
Intel® Xeon® Processor D Product Family Technical Overview
By David Mulnix (Intel)Posted 05/22/20150
Contents 1. Form Factor Overview2. Intel® Xeon® Processor D Product Family Overview3. Intel® Xeon® Processor D Product Family Feature Overview4. Intel® Xeon® processor D Product Family introduces new instructions as well as enhancements of previous instructions45. Intel® Advanced Vector Extensio...
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Elusive Algorithms - Parallel Scan
By jimdempseyatthecove Posted on 05/22/15 1
Last month there was a query on the IDZ MIC forum "how to perform inclusive scan in C cilk" in which my initial reply was: Parallelizing this is problematic due to the next result being dependent upon the prior result. While this is not impossible, it is rather difficult and it introduces some r...
Advanced Computer Concepts for the (Not So) Common Chef: The Home Kitchen
By Taylor Kidd (Intel) Posted on 05/15/15 0
Since that brief aside on terminology is out of the way, let us continue with the kitchen analogy. For the Intel® Xeon Phi™ family of products, and indeed for any processor, one of its cores is like a kitchen. The components of the processor pipeline (ALU, Instruction Decoder, Memory Cluster, et...
Making programmers more productive
By BELINDA A. (Intel) Posted on 05/12/15 0
A preview of the latest developer tools from Intel that help increase programmer productivity.
Accelerating Business Intelligence and Insights with Software Optimized for the Intel® Xeon® Processor E7 v3 Family
By Mike Pearce (Intel) Posted on 05/12/15 0
By Mike Pearce, Ph.D. Intel Developer Evangelist for the IDZ Server Community. On May 5, 2015, Intel Corporation announced the release of its highly anticipated Intel® Xeon® processor E7 v3 family.  One key area of focus for the new processor family is that it is designed to accelerate business ...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Memory access pattern for threads
By Sangamesh B.1
      I've one basic question on threads memory access pattern. Suppose the computer/system/node has two sockets, each socket has its own block of memory(shared among two sockets), each socket has 4 cores. If there are two threads running(forked from a single process, may be pthreads/openmp threads), and thread 1 is on socket 1 and thread 2 on socket 2. If thread 1 tries to access data from socket 2's block of memory, then whether access time for this is same as accessing the data from its own block of memory or different? 
Set OpenMP attributes within code
By Allen Barnett2
Hi: I have discovered that setting KMP_BLOCKTIME=0 results in the best performance of my Fortran code. (Not by much, really, but it is measurable over our entire test suite.) Is it possible to set this attribute through an API call? I don't want to depend on the end user having to set environment variables. Also related, there are some loops for which the GCC GOMP library gives the best results when the scheduling is declared as "guided". When compiled with the Intel compiler, however, it appears best to not declare the schedule as guided. Is there an API function which can control the schedule for a given loop? Thanks, Allen  
Haswell Transactional Memory read/write-set information
By YangHun P.1
Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX). As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly) Then, Can I track transactional memory operations and get information like address, and values of read/write-set?
I have a problem with igzip
By gq L.2
Hi! I am studying about compression algorithm and software. I have question about igzip. I download igzip library in intel homepage. But I don`t know how to make wrapper. Can you send me 'example of wrapper' or 'example code' or 'manual'? I read homepage and saw a simple application. I don`t know how to input target file for compression and to output compression file and how to decompression? Do I make code about 'fast_lz and init_stream' function by myself? Plz help me. thank you
PCM reporting lower than expected memory read counts
By Patrick L.2
I have a piece of code on which I'm running PCM (Performance Counter Monitor). It is essentially the following: uint64_t *a,*b; a = new uint64_t[LEN]; b = new uint64_t[LEN]; for( int i=0;i<LEN;i++ ) a[i] = b[i];With LEN set to 402,653,184 (384 Mi), PCM is reporting 0.72 GB under READ and 6.30 GB under WRITE. Given that each array is 3 GiB, I would expect that both arrays would be read (since processor uses write-allocate), giving a READ of about 6 GiB. I would expect array "a" to be written back, giving a write count of 3 GiB. Does anyone know why the read count is so low, and the write count is higher than expected? Processor is Intel Core i7 940 (Nehalem). Any help is appreciated. Patrick
igzip 'make' problem
By gq L.2
Hi   I download and modify YASM path of Makefile   but it doesn`t make .exe file   I don`t know igzip execution sequence   If you have document about igzip, plz share it.   Thank you
igzip 'make' problem
By gq L.1
Hi I download and modify YASM path of Makefile but it don`t make .exe file I don`t know igzip execution sequence If you have document about igzip, plz share it. Thank you
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