Search

Search Results for:

Search Results: 43

  1. pcm tools for DIMMs

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/472408

    Sep 7, 2013 ... Hi, With PCM, we can monitor channel read and writes. ... be mapped to the same rank in all DRAM channels, since channel interleaving on ...

  2. SB-E memory read bandwidth limitation?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/530614

    Sep 4, 2014 ... If 1 64 bit memory channel were able to transfer 64 bits on every cycle of the ..... If you are running with channel interleave disabled, then large ...

  3. Performance loss migrating from Xeon X5550 to Xeon E5-2650 v2

    https://software.intel.com/en-us/forums/intel-clusters-and-hpc-technology/topic/611068

    Feb 29, 2016 ... One difference is in DRAM channel interleaving. ... The Xeon E5-2670 and Xeon E5-2640 v2 both use four memory channels per socket, and ...

  4. Planar vs. Interleaved and Processing Speed Question (IPP + TBB)

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/628566

    Apr 29, 2016 ... RGB pixel data is typically stored in both the planar and interleaved ... And if you process channel-by-channel you have the advantage of ...

  5. FFT with different memory layout

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/283957

    May 6, 2011 ... ... with data (always 2 channels stereo) ordered as left-right-left-right-. ... between interleaved two channel data and two channel planar data.

  6. Copy | Intel® Software

    https://software.intel.com/en-us/node/503752

    Case 3: Copying a selected channel in a multi-channel image .... You can also use the ippiCopy function to convert the interleaved color image into separate ...

  7. How Memory Is Accessed | Intel® Software

    https://software.intel.com/en-us/articles/how-memory-is-accessed

    Jun 15, 2016 ... If the Multi-Channel DRAM (MCDRAM) is used to cache the DIMMs, that ... Physical addresses can interleave across sockets, or just within a ...

  8. using ippiAlphaComp with separate RGB and A buffers

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/660135

    Jul 7, 2016 ... so I gather that I need to interleave the alpha and RGB images... ... channel from an 8u_C1R image into just one channel of an 8u_C4R image?

  9. Processor and DRAM Power Measurement Platform

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/389149

    Apr 17, 2013 ... 022, chipset: 20 MCHBAR: MAD—Address decode channel 0: HORIAddr High Order Rank Interleave Address. Specifies which DIMM address ...

  10. Can someone explain how NUMA is not always best for multi-socket ...

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/392519

    May 13, 2013 ... ... -ep-numa-versus-interleaved-memory-aka-suma-there-is-no-difference .... but a single thread should use various QPI channels about evenly.

  11. IPP Function to convert from raw 8-bit RGB to 24-bit full RGB values?

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/307745

    Dec 16, 2005 ... Basically, as I can see,you need to split interleaved color channels into planes and after that to interleave them again in RGBRGBRGB order.

  12. Download

    https://software.intel.com/sites/default/files/ef/29/26146

    Nov 28, 2001 ... The casts performed on each R, G, B channel for diffuse and specular lighting in Listing ..... interleave mm1 = specular2, diffuse2 movq mm2 ...

  13. Single Threaded Memory Bandwidth on Sandy Bridge

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/480004

    Oct 18, 2013 ... A BIOS that doesn't interleave RAM could cause all requests to come from the same channel, reducing the peak bandwidth to 25% off the bat.

  14. Intel® MKL NUMA Notes | Intel® Software

    https://software.intel.com/en-us/articles/intel-mkl-numa-notes

    Aug 2, 2012 ... If cores across NUMA nodes will be employed for the program, interleaved memory mapping can be considered where memory is allocated on ...

  15. SSE vs AVX optimized code generation

    https://software.intel.com/pt-br/forums/intel-c-compiler/topic/326004

    Originally the code was written with the 'interleave' variable in the mathops class set as a ... Data set size: 32smps/channel (= 256 bytes per channel) All times ...

  16. Independent Channel vs. Lockstep Mode – Drive your Memory ...

    https://software.intel.com/en-us/blogs/2014/07/11/independent-channel-vs-lockstep-mode-drive-you-memory-faster-or-safer

    Jul 11, 2014 ... Each Intel® SMI2 link is then connected to a Intel® C102/C104 Scalable Memory Buffer, which in return provides two memory channels.

  17. Intel(R) AMT SDK Implementation and Reference Guide

    https://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/HTMLDocuments/WS-Management_Class_Reference/AMT_TLSProtocolEndpoint.htm

    ... Transp HDLC, Interleave Channel, FAST Channel, IP (for APPN HPR in IP Networks), CATV MAC Layer, CATV Downstream, CATV Upstream, Avalon 12MPP ...

  18. Single-threaded memory performance for dual socket Xeon E5 ...

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/509237

    Apr 11, 2014 ... ... system has only 2 DRAM channels (providing 21.33 GB/s peak BW), .... but the system booted with a non-optimal memory interleaving, and I ...

  19. Multidimensional Transpose -- Prefetching

    https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/581589

    Aug 12, 2015 ... My Xeon E5-2680 v2 systems have 2 dual-rank DIMMs per channel and .... So you could interleave stores to four different cache lines, but if you ...

  20. Performance Analysis Guide

    https://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf

    Threading Technology (HT), allowing the hardware to interleave instructions of .... Intel® Xeon™ 550 processor has a 3 channel integrated memory controller.

For more complete information about compiler optimizations, see our Optimization Notice.