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  1. pcm tools for DIMMs

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/472408

    Sep 7, 2013 ... Hi, With PCM, we can monitor channel read and writes. ... be mapped to the same rank in all DRAM channels, since channel interleaving on ...

  2. How Memory Is Accessed | Intel® Software

    https://software.intel.com/en-us/articles/how-memory-is-accessed

    Jun 15, 2016 ... If the Multi-Channel DRAM (MCDRAM) is used to cache the DIMMs, that ... Physical addresses can interleave across sockets, or just within a ...

  3. Performance loss migrating from Xeon X5550 to Xeon E5-2650 v2

    https://software.intel.com/en-us/forums/intel-clusters-and-hpc-technology/topic/611068

    One difference is in DRAM channel interleaving. The Xeon X5550 has 3 DRAM channels and interleaves consecutive cache lines around the 3 ...

  4. wish: IIR filtering of multi-channel sample (IIROne_P())

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/280596

    Dec 9, 2011 ... could take a single vector of multi-channel data containing just one time sample from each channel. Some call this "interleaved" data.

  5. FFT with different memory layout

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/283957

    May 6, 2011 ... ... with data (always 2 channels stereo) ordered as left-right-left-right-. ... between interleaved two channel data and two channel planar data.

  6. SB-E memory read bandwidth limitation?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/530614

    Sep 4, 2014 ... If 1 64 bit memory channel were able to transfer 64 bits on every cycle ... If you are running with channel interleave disabled, then large pages ...

  7. Copy | Intel® Software

    https://software.intel.com/en-us/node/503752

    Case 3: Copying a selected channel in a multi-channel image .... You can also use the ippiCopy function to convert the interleaved color image into separate ...

  8. Independent Channel vs. Lockstep Mode – Drive your Memory ...

    https://software.intel.com/en-us/blogs/2014/07/11/independent-channel-vs-lockstep-mode-drive-you-memory-faster-or-safer

    Jul 11, 2014 ... In particular, only one memory channel is driving an Intel®SMI2 link, as opposed to two in independent channel mode. Furthermore, the Intel® ...

  9. Planar vs. Interleaved and Processing Speed Question (IPP + TBB)

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/628566

    Apr 29, 2016 ... Planar vs. Interleaved and Processing Speed Question (IPP + TBB) ... Try sharpening the Y channel only, that may give good results. Regards,.

  10. Processor and DRAM Power Measurement Platform

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/389149

    Apr 17, 2013 ... 022, chipset: 20 MCHBAR: MAD—Address decode channel 0: HORIAddr High Order Rank Interleave Address. Specifies which DIMM address ...

  11. DPDK Performance Optimization Guidelines White Paper | Intel ...

    https://software.intel.com/en-us/articles/dpdk-performance-optimization-guidelines-white-paper

    Aug 9, 2016 ... Be sure to make correct use of the channel parameter. For example, use CHANNEL PARAMETER N = 3 for a 3 channel memory system.

  12. using ippiAlphaComp with separate RGB and A buffers

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/660135

    Jul 7, 2016 ... so I gather that I need to interleave the alpha and RGB images... ? convert ... function - shift pDst pointer to A-channel position and use your ...

  13. Intel® MKL NUMA Notes | Intel® Software

    https://software.intel.com/en-us/articles/intel-mkl-numa-notes

    Aug 2, 2012 ... If cores across NUMA nodes will be employed for the program, interleaved memory mapping can be considered where memory is allocated on ...

  14. Single Threaded Memory Bandwidth on Sandy Bridge

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/480004

    A BIOS that doesn't interleave RAM could cause all requests to come from the same channel, reducing the peak bandwidth to 25% off the bat.

  15. Can someone explain how NUMA is not always best for multi-socket ...

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/392519

    ... -ep-numa-versus-interleaved-memory-aka-suma-there-is-no-difference .... but a single thread should use various QPI channels about evenly.

  16. Fast Color Conversion Using SSE & MMX(tm) Technology

    https://software.intel.com/sites/default/files/ef/29/26146

    Nov 28, 2001 ... The casts performed on each R, G, B channel for diffuse and specular lighting in Listing ..... interleave mm1 = specular2, diffuse2 movq mm2 ...

  17. IPP Function to convert from raw 8-bit RGB to 24-bit full RGB values?

    https://software.intel.com/en-us/forums/intel-integrated-performance-primitives/topic/307745

    Dec 16, 2005 ... Basically, as I can see,you need to split interleaved color channels into planes and after that to interleave them again in RGBRGBRGB order.

  18. SSE vs AVX optimized code generation

    https://software.intel.com/en-us/forums/intel-c-compiler/topic/326004

    Originally the code was written with the 'interleave' variable in the mathops class ... Data set size: 32smps/channel (= 256 bytes per channel)

  19. Single-threaded memory performance for dual socket Xeon E5 ...

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/509237

    Apr 11, 2014 ... ... system has only 2 DRAM channels (providing 21.33 GB/s peak BW), .... but the system booted with a non-optimal memory interleaving, and I ...

  20. Multidimensional Transpose -- Prefetching

    https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/581589

    If you have one dual-rank DIMM per channel, that provides 2x8=16 .... So you could interleave stores to four different cache lines, but if you tried ...

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