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  1. Transactional Synchronization in Haswell | Intel® Software

    https://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell

    Feb 7, 2012 ... Intel has released details of Intel® Transactional Synchronization Extensions ( Intel® TSX) for the future multicore processor code-named ...

  2. Haswell New Instruction Descriptions Now Available! | Intel® Software

    https://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available

    Jun 13, 2011 ... Arriving first in our 2013 Intel microarchitecture codename “Haswell”, the new instructions accelerate a broad category of applications and ...

  3. Events for Intel(R) Microarchitecture Code Name Haswell | Intel ...

    https://software.intel.com/en-us/node/589935

    Events for Intel(R) Microarchitecture Code Name Haswell. This section provides reference for hardware events that can be monitored for the CPU(s):.

  4. temporary pcie bandwidth drops on Haswell-v3

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/600913

    With the SandyBridge-v1/IvyBridge-v2 architecture everything worked fine. Now with the new Haswell-v3 servers we have the following problem:

  5. 4th Generation Intel® Core™ Processor (Haswell) Overview | Intel ...

    https://software.intel.com/en-us/videos/4th-generation-intel-core-processor-haswell-overview?language=ru

    Jun 3, 2013 ... Jim Fister of Intel gives an overview of the 4th Generation Intel® Core™ Processor Family (code name Haswell). Jim covers the performance, ...

  6. Uncore frequency on Haswell

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/543513

    Can someone explain how the processor controls the uncore frequency. I understand that on Haswell microarchitecture, the uncore is on a ...

  7. Write your first program with Haswell new instructions | Intel® Software

    https://software.intel.com/en-us/blogs/2012/06/04/write-your-first-program-with-haswell-new-instructions

    Jun 4, 2012 ... It has been almost a year since the Haswell new instructions have been announced by Intel. Even though silicon is not generally available yet, ...

  8. How to count L1 cache miss/hit on Intel Haswell 4790?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/610581

    With intel PCM I can count L2 and L3 cache misses and hits. however, it cannot count for L1 cache. how to count L1 events on haswell 4790?

  9. Haswell GFLOPS

    https://software.intel.com/en-us/forums/intel-isa-extensions/topic/394248

    Hi Intel Experts: I cannot find the latest Intel Haswell CPU GFlops, could you please let me know that? I want to understand the performance ...

  10. NEW Graphics Driver 15.36.19.4170 posted for Haswell and ...

    https://software.intel.com/en-us/blogs/2015/06/02/new-graphics-driver-1536194170-posted-for-haswell-and-broadwell

    Jun 2, 2015 ... See the Release Notes for additional details. The 15.36.19.4170 has been posted to Intel Download Center at the following direct links to the ...

  11. FLOPS measurement on Haswell-EP and Broadwell-EP

    https://software.intel.com/en-us/forums/intel-vtune-amplifier-xe/topic/700255

    Oct 20, 2016 ... Hi, I am trying to measure the number of FLOPS my application achieves on Haswell-EP and Broadwell-EP with VTune 2017 in order to figure ...

  12. Events for Intel(R) Microarchitecture Code Name Haswell EP | Intel ...

    https://software.intel.com/en-us/node/589936

    Events for Intel(R) Microarchitecture Code Name Haswell EP. This section provides reference for hardware events that can be monitored for the CPU(s):. Intel(R) ...

  13. HHVM and Haswell | Intel® Software

    https://software.intel.com/en-us/blogs/2015/09/28/hhvm-and-haswell

    Sep 28, 2015 ... There is no question that PHP is the most popular language in use today to implement server code on web pages. Something like 80% of web ...

  14. L1-, L2- and L3-bandwidth of E5-2680 v3 (ie, Haswell)

    https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/608964

    Feb 4, 2016 ... Hi all, I am currently investigating the L1, L2 and L3 bandwidth of our latest Haswell CPU (Xeon E5-2680 v3). The L1, L2 and L3 size of this ...

  15. Inconsistent L2 HW Prefetch behavior on Haswell

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/592464

    I was running some microbenchmarks on a Xeon E5-2660 v3 system and came across some very odd behavior in the L2 streaming prefetcher.

  16. Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/532346

    Hello, I'm having problems achieving the 64 bytes/cycle L2 to L1 cache bandwidth on the Haswell core. I can only achieve 32 bytes/cycle.

  17. An Introduction to the 4th Generation Intel® Core™ Processor | Intel ...

    https://software.intel.com/en-us/articles/an-introduction-to-the-intel-4th-generation-core-processor

    May 29, 2013 ... Intel is launching the 4th generation Intel® Core™ processor, code-named Haswell. Its capabilities build on the 3rd generation Intel® Core™ ...

  18. Using RAPL to read PP0 and DRAM energy on haswell

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/623642

    Apr 5, 2016 ... I am trying to use that to read the Package energy and the DRAM and PP0 on a server mother board for a E5-2620 v3 (a Haswell xeon with 6 ...

  19. How to detect New Instruction support in the Haswell/Broadwell ...

    https://software.intel.com/en-us/forums/intel-isa-extensions/topic/698434

    Oct 3, 2016 ... What I am looking for is a feedback and may be an updated piece of code to detect the support for the new ISA in the haswell/broadwell ...

  20. Optimizing Big Data processing with Haswell 256-bit Integer SIMD ...

    https://software.intel.com/en-us/blogs/2014/06/11/optimizing-big-data-processing-with-haswell-256-bit-integer-simd-instructions

    Jun 11, 2014 ... Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer ...

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