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  1. Intel® Memory Latency Checker v3.1a | Intel® Software

    https://software.intel.com/en-us/articles/intelr-memory-latency-checker

    It is challenging to accurately measure memory latencies on modern Intel processors as they have sophisticated h/w prefetchers. Intel® MLC automatically  ...

  2. Avoiding Memory Leaks in Intel MKL | Intel® Software

    https://software.intel.com/en-us/node/528564

    When running, Intel MKL allocates and deallocates internal buffers to facilitate better performance. However, in some cases this behavior may result in memory  ...

  3. Memory Access Analysis | Intel® Software

    https://software.intel.com/en-us/memory-access-analysis-lin

    Use the Intel® VTune™ Amplifier's Memory Access analysis to identify memory- related issues, like NUMA problems and bandwidth-limited accesses, and ...

  4. Monitoring Integrated Memory Controller Requests in the 2nd, 3rd ...

    https://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel

    The counters employ circuitry residing in the memory controller, and monitor transaction requests coming from various sources, e.g. the processor cores, the ...

  5. Intel® Inspector | Intel® Software

    https://software.intel.com/en-us/intel-inspector-xe

    Intel® Inspector is a dynamic memory and threading error checking tool for C, C++, C# and Fortran applications that run on Windows* and Linux*.

  6. The Intel SGX Memory Encryption Engine | Intel® Software

    https://software.intel.com/en-us/blogs/2016/02/26/memory-encryption-an-intel-sgx-underpinning-technology

    Feb 26, 2016 ... Intel SGX has had to break ground in many areas. One of these was how to protect memory outside of the processor package.

  7. Invalid Partial Memory Access | Intel® Software

    https://software.intel.com/en-us/node/622542

    Occurs when a read or write instruction references a block (2-bytes or more) of memory where part of the block is logically invalid.

  8. Eliminate Memory Errors and Improve Program Stability

    https://software.intel.com/sites/products/evaluation-guides/docs/studioxe-evalguide-remove-memory-errors.pdf

    Eliminate Memory. Errors and Improve. Program Stability with Intel® Parallel Studio XE. INTEL® PARALLEL STUDIO XE EVALUATION GUIDE ...

  9. How Memory Is Accessed | Intel® Software

    https://software.intel.com/en-us/articles/how-memory-is-accessed

    Jun 15, 2016 ... This article explains why optimal usage of the memory subsystem can have massive performance benefits.

  10. Memory Limits for Applications on Windows* | Intel® Software

    https://software.intel.com/en-us/articles/memory-limits-applications-windows

    May 16, 2011 ... A discussion of limits on the size of code and data for applications running on 32- bit and 64-bit Windows systems.

  11. Interpreting Memory Usage Data | Intel® Software

    https://software.intel.com/en-us/node/544170

    HPC Performance Characterization analysis with the Analyze memory bandwidth option enabled. When the analysis is complete, the Intel® VTune™ Amplifier ...

  12. __local Memory | Intel® Software

    https://software.intel.com/en-us/node/540449

    OpenCL™ Optimization Guide for Intel® Processor Graphics. Local memory can be used to avoid multiple redundant reads from and writes to global memory.

  13. OpenCL 2.0 Shared Virtual Memory Code Sample | Intel® Software

    https://software.intel.com/en-us/articles/opencl-20-shared-virtual-memory-code-sample

    This sample demonstrates the fundamentals of using Shared Virtual Memory ( SVM) capabilities in OpenCL™ applications. The SVM Basic code sample uses ...

  14. Introduction to Intel® Memory Protection Extensions | Intel® Software

    https://software.intel.com/en-us/articles/introduction-to-intel-memory-protection-extensions

    Jul 16, 2013 ... The C and C++ languages provide for memory access via pointers, however, these languages do not ensure the safe use of pointers.

  15. Memory Allocation and First-Touch | Intel® Software

    https://software.intel.com/en-us/articles/memory-allocation-and-first-touch

    Memory allocation is expensive on the coprocessor compared to the Intel® Xeon processor so it is prudent to reuse already-allocated memory wherever ...

  16. Address Range Partial Memory Mirroring | Intel® Software

    https://software.intel.com/en-us/articles/address-range-partial-memory-mirroring

    Jan 5, 2016 ... Operating System Interface Specification Contents IntroductionPresenting Mirrored Memory to OS—Boot TimeRuntime Hot-Added/Removed ...

  17. Intel® IPP Memory Function ippMalloc/Free FAQ | Intel® Software

    https://software.intel.com/en-us/articles/performance-tools-for-software-developers-memory-function-faq

    Aug 12, 2016 ... Information about Intel® Integrated Performance Primitives (Intel® IPP) memory functions.

  18. An Intro to MCDRAM (High Bandwidth Memory) on Knights Landing ...

    https://software.intel.com/en-us/blogs/2016/01/20/an-intro-to-mcdram-high-bandwidth-memory-on-knights-landing

    Jan 20, 2016 ... Intel's next generation Xeon Phi™ processor family x200 product (code-named Knights Landing) brings in new memory technology, a high ...

  19. Shared Memory Control | Intel® Software

    https://software.intel.com/en-us/node/528822

    I_MPI_SHM_CACHE_BYPASS Control the message transfer algorithm for the shared memory. Syntax I_MPI_SHM_CACHE_BYPASS= Arguments Binary ...

  20. Mapping Memory Objects | Intel® Software

    https://software.intel.com/en-us/node/540453

    Host code shares physical memory with both OpenCL™ devices: the CPU and the Intel® Graphics. So consider using combination of clEnqueueMapBuffer and  ...

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