Search

Search Results for:

Search Results: 437

  1. How to use MTRR on machines with Skylake processors?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/720897

    Mar 16, 2017 ... I'm trying to do some memory management on xen-4.5.0 on machines with Skylake processors, and get confused with something about ...

  2. TLB, large pages and prefetching

    https://software.intel.com/en-us/search/gss/mtrr?page=2

    Jul 31, 2013 ... So if you mark a memory region as uncacheable (using either an MTRR or the PTEs), the memory controller will still read 64 Bytes from the .

  3. cache write back for pci device

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/393070

    Basically I confirmed what the SDM says about cache except that when I set both PAT and MTRR to write back, the linux kernel went to a fatal ...

  4. Linux ffmpeg-qsv return MFX_ERR_UNSUPPORTED

    https://software.intel.com/en-us/search/gss/mtrr?page=3

    Apr 2, 2015 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx .

  5. Português

    https://software.intel.com/pt-br/search/gss/mtrr

    https://software.intel.com/pt-br/search/gss/mtrr. Feb 29, 2012 ... ... pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe  ...

  6. Buscar | Software Intel®

    https://software.intel.com/es-es/search/gss/mtrr?page=2

    24 Ene 2009 ... ... msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl .

  7. Cache Enabled/Disabled?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/278571

    Apr 27, 2012 ... Myassumption is that ifthe MTRR and PAT are writeback and Iset the CD&NW bits of CR0 then all levels of cacheare disabled. But if I clear the ...

  8. 0 vendor_id : GenuineIntel cpu family : 6 model

    https://software.intel.com/sites/default/files/forum/377784/proc-cpuinfo.txt

    ... pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon ...

  9. cl_khr_fp64 unsupported message on Xeon processor

    https://software.intel.com/pt-br/node/632400

    May 16, 2016 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts mmx fxsr sse sse2 ss ht syscall nx rdtscp lm ...

  10. Monitoring PCIe Data for Xeon E5-2600

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/500900

    Feb 2, 2014 ... Some sub-regions of the IO hole address range will have an MTRR of WC (Write Combining), but that is also an uncached memory type.

  11. Is it possible to access RAM directly while the memory is cached?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/419444

    Immediately, I modified the current core's MTRR to set the physical memory location of X into UC. Finally, X is read and the result is still 1.

  12. Compiling gsl 1.15 with Intel 12.1

    https://software.intel.com/en-us/forums/intel-c-compiler/topic/279461

    Feb 29, 2012 ... ... pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs ...

  13. Make sure certain PCIe writes are 64bytes to improve the bus ...

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/685125

    Sep 13, 2016 ... Note that the memory type depends on both the MTRR and the PAT for the address in question. This is described in Chapter 11 of Volume 3 of ...

  14. EPT write back memory type and Machine Check exception

    https://software.intel.com/en-us/forums/virtualization-software-development/topic/282254

    Aug 24, 2011 ... When setting up EPT paging structures, software should make sure the EPT memory-type in the EPT entry matches the MTRR value for the ...

  15. Write Combine Performance and Out of Order

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/518062

    The device driver set IO memory region using ioremap_wc (MTRR). This IO memory is the non prefetchable region. The PAT can be set with ...

  16. Cache-references and Cache-misses counters

    https://software.intel.com/en-us/forums/intel-performance-tuning-utility/topic/288159

    Aug 16, 2010 ... I hope this is an appropriate place to post my question.Using the linux /proc/mtrr i have configured all physical memory space to be uncachable.

  17. non-cached memory impact on platform power consumption

    https://software.intel.com/pt-br/forums/software-tuning-performance-optimization-platform-monitoring/topic/498425

    24 dez. 2013 ... What is the impact of allocating non-cached memory by the driver but still using snoop enabled DMA to this memory region (as per MTRR or ...

  18. Does VTune work with AMD Opteron processor?

    https://software.intel.com/en-us/forums/intel-vtune-amplifier-xe/topic/309160

    Feb 24, 2005 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext lm 3dnowext ...

  19. Poor cache performance on Tigerton quad-core

    https://software.intel.com/pt-br/forums/intel-vtune-amplifier-xe/topic/304259

    Nov 2, 2007 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm ...

  20. gsl installation with intel compilers

    https://software.intel.com/en-us/forums/intel-c-compiler/topic/291743

    Feb 1, 2010 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm ...

For more complete information about compiler optimizations, see our Optimization Notice.