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Intel® 64 Architecture Processor Topology Enumeration

Download Code Package: 20160519-cpuid_topo.tar.gz
Authored by Last updated on 07/05/2019 - 20:39
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Single-Producer/Single-Consumer Queue

Unbounded single-producer/single-consumer queue. Internal non-reducible cache of nodes is used. Dequeue operation is always wait-free. Enqueue operation is wait-free in common case. No atomic RMW operations nor heavy memory fences are used.
Authored by Dmitry Vyukov Last updated on 12/12/2018 - 18:00
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Improving Averaging Filter Performance Using Intel® Cilk™ Plus

Intel® Cilk™ Plus is an extension to the C and C++ languages to support data and task parallelism.  It provides three new keywords to i

Authored by Anoop M. (Intel) Last updated on 12/12/2018 - 18:00
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Eight Optimizations for 3-Dimensional Finite Difference (3DFD) Code with an Isotropic (ISO)

This article describes how to implement and optimize a three-dimension isotropic kernel with finite differences to run on the Intel® Xeon® Processor and Intel® Xeon Phi™.
Authored by Cédric ANDREOLLI (Intel) Last updated on 07/06/2019 - 16:40
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Caffe* Training on Multi-node Distributed-memory Systems Based on Intel® Xeon® Processor E5 Family

Caffe is a deep learning framework developed by the Berkeley Vision and Learning Center (BVLC) and one of the most popular community frameworks for image recognition. Caffe is often used as a benchmark together with AlexNet*, a neural network topology for image recognition, and ImageNet*, a database of labeled images.
Authored by Gennady F. (Blackbelt) Last updated on 07/05/2019 - 14:54
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Putting Your Data and Code in Order: Optimization and Memory – Part 1

This series of two articles discusses how data and memory layout affect performance and suggests specific steps to improve software performance. The basic steps shown in these two articles can yield significant performance gains. These two articles are designed at an intermediate level. It is assumed the reader desires to optimize software performance using common C, C++ and Fortran* programming...
Authored by David M. Last updated on 12/12/2018 - 18:00
Article

Code Sample: Allocate Memory Efficiently on an Intel® Xeon Phi™ Processor

How to efficiently use Multi-Channel DRAM (MCDRAM) and synchronous dynamic random-access memory.
Authored by Mike P. (Intel) Last updated on 07/06/2019 - 16:40
Article

整理您的数据和代码: 优化和内存 — 第 1 部分

This series of two articles discusses how data and memory layout affect performance and suggests specific steps to improve software performance. The basic steps shown in these two articles can yield significant performance gains. These two articles are designed at an intermediate level. It is assumed the reader desires to optimize software performance using common C, C++ and Fortran* programming...
Authored by David M. Last updated on 12/12/2018 - 18:00
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Приводим данные и код в порядок: оптимизация и память, часть 1

This series of two articles discusses how data and memory layout affect performance and suggests specific steps to improve software performance. The basic steps shown in these two articles can yield significant performance gains. These two articles are designed at an intermediate level. It is assumed the reader desires to optimize software performance using common C, C++ and Fortran* programming...
Authored by Last updated on 12/12/2018 - 18:00
Article

Improve Application Performance on an Intel® Xeon Phi™ Processor

Learn techniques for vectorizing code, adding thread-level parallelism, and enabling memory optimization.
Authored by Nguyen, Loc Q (Intel) Last updated on 06/14/2019 - 11:50