Article

Programming and Compiling for Intel® Many Integrated Core Architecture

This article discussions parallelization and provides links that will help you understand your programming environment and evaluate the suitability of your app.
Authored by AmandaS (Intel) Last updated on 03/26/2019 - 10:07
Article

Efficient Parallelization

This article is part of the Intel® Modern Code Developer Community documentation which supports developers in leveraging application performance in code through a systematic step-by-step optimization framework methodology. This article addresses: Thread level parallelization.
Authored by Ronald W Green (Blackbelt) Last updated on 03/21/2019 - 12:00
Article

Parallelization Using Intel® MPI

Get an overview of parallelization using the Intel® MPI Library and links to additional documentation.
Authored by admin Last updated on 03/21/2019 - 12:00
Article

Measuring performance in HPC

This is the first article in a series of articles about High Performance Computing with the Intel® Xeon Phi™ coprocessor.

Authored by Last updated on 07/06/2019 - 16:10
Blog post

Advanced Computer Concepts for the (Not So) Common Chef: The Home Kitchen

Since that brief aside on terminology is out of the way, let us continue with the kitchen analogy.

Authored by Last updated on 07/06/2019 - 17:10
Article

Optimizing Legacy Molecular Dynamics Software with Directive-based Offload

Directive-based programming models are one solution for exploiting many-core coprocessors to increase simulation rates in molecular dynamics.

Authored by WILLIAM B. (Intel) Last updated on 03/21/2019 - 12:00
Article

Putting Your Data and Code in Order: Data and layout - Part 2

Apply the concepts of parallelism and distributed memory computing to your code to improve software performance. This paper expands on concepts discussed in Part 1, to consider parallelism, both vectorization (single instruction multiple data SIMD) as well as shared memory parallelism (threading), and distributed memory computing.
Authored by David M. Last updated on 07/06/2019 - 16:40
Article

How to detect Knights Landing AVX-512 support (Intel® Xeon Phi™ processor)

The Intel® Xeon Phi™ processor, code named Knights Landing, is part of the second generation of Intel Xeon Phi products. Knights Landing supports Intel® AVX-512 instructions, specifically AVX-512F (foundation), AVX-512CD (conflict detection), AVX-512ER (exponential and reciprocal) and AVX-512PF (prefetch).
Authored by James R. (Blackbelt) Last updated on 06/14/2019 - 11:50
Article

Приводим данные и код в порядок: данные и разметка, часть 2

In this pair of articles on performance and memory covers basic concepts to provide guidance to developers seeking to improve software performance. This paper expands on concepts discussed in Part 1, to consider parallelism, both vectorization (single instruction multiple data SIMD) as well as shared memory parallelism (threading), and distributed memory computing.
Authored by David M. Last updated on 07/06/2019 - 16:40
Article

Classical Molecular Dynamics Simulations with LAMMPS Optimized for Knights Landing

LAMMPS is an open-source software package that simulates classical molecular dynamics. As it supports many energy models and simulation options, its versatility has made it a popular choice. It was first developed at Sandia National Laboratories to use large-scale parallel computation.
Authored by WILLIAM B. (Intel) Last updated on 03/21/2019 - 12:00