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Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

Authored by gaston-hillar (Blackbelt) Last updated on 07/06/2019 - 17:00
Blog post

Experimenting with OpenStack* Sahara* on Docker* Containers

Docker* is an emerging technology that has become very popular recently in the market. It provides a flexible architecture to deploy applications. OpenStack* is another hot technology on the market. It has been available for several years, became more stable and also added more features support in recent releases.
Authored by WEITING C. (Intel) Last updated on 07/06/2019 - 17:10
Article

Intel® Xeon® Processor E7 v3 Product Family

Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Intel® Parallel Computing Center at Georgia Institute of Technology

The Intel® Parallel Computing Center (Intel® PCC) on Big Data in Biosciences and Public Health is focused on developing and optimizing parallel algorithms and software on Intel® Xeon® Processor and Intel® Xeon Phi™ Coprocessor systems for handling high-throughput DNA sequencing data and gene expression data.
Authored by admin Last updated on 11/14/2017 - 08:27
Blog post

Academics Make Games Better - Foundations of Digital Games 2015

Foundations of Digital Games is a summit of innovators and influencers in gaming-related academia as well as the games industry itself. In what was originally “the premier educational conference for faculty who use game development to teach computer science concepts and principles”, it began in 2006 as Microsoft Academic Days on Game Development in Computer Science Education (GDCSE) and was...
Authored by Last updated on 01/24/2018 - 12:12
Blog post

The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Authored by David S. (Blackbelt) Last updated on 07/04/2019 - 20:00
Article

Caffe* Training on Multi-node Distributed-memory Systems Based on Intel® Xeon® Processor E5 Family

Caffe is a deep learning framework developed by the Berkeley Vision and Learning Center (BVLC) and one of the most popular community frameworks for image recognition. Caffe is often used as a benchmark together with AlexNet*, a neural network topology for image recognition, and ImageNet*, a database of labeled images.
Authored by Gennady F. (Blackbelt) Last updated on 07/05/2019 - 14:54
Article

IDF'15 Webcast: Data Analytics and Machine Learning

This Technology Insight will demonstrate how to optimize data analytics and machine learning workloads for Intel® Architecture based data center platforms. Speaker: Pradeep Dubey Intel Fellow, Intel Labs Director, Parallel Computing Lab, Intel Corporation
Authored by Mike P. (Intel) Last updated on 07/06/2019 - 16:40
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Proof Points for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

Cache Allocation Technology (CAT) provides benefits across a number of usages, as described in the previous article in this series. This article briefly describes one proof point from the data center (prioritizing a web server to improve its performance) and one from communications (protecting a key communications infrastructure virtual machine (VM)).
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40