Blog post

Optimization of Data Read/Write in a Parallel Application

(This work was done by Vivek Lingegowda during his internship at Intel.)

Authored by Last updated on 07/04/2019 - 17:40
Blog post

Rainbows, Unicorns and Performance Portability

An old Jewish fable tells about a poor man asking for advice from the rabbi. The family is large, the house is small, and it feels very crowded.

Authored by Last updated on 12/12/2018 - 18:08
Blog post

The Unfairness of Good Syntax

The unfairness of good syntax - bad syntax is a problem; good syntax is not a solution.
Authored by Last updated on 07/04/2019 - 11:17
Article

Second Generation Intel® Xeon® Processor Scalable Family Technical Overview

New features and enhancements available in the second generation Intel® Xeon® processor Scalable family and how developers can take advantage of them
Authored by David Mulnix (Intel) Last updated on 09/30/2019 - 17:28
Article

Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:28
Article

Analysis and Optimization of Financial Analytics Benchmark on Modern Multi- and Many-core IA-Based Architectures

By Mikhail Smelyanskiy, Jason Sewall, Dhiraj D.

Authored by Belinda Liviero (Intel) Last updated on 10/02/2019 - 13:38
Article
Article

Intel Solutions and Technologies for the Evolving Data Center

  One Stop for Optimizing Your Data Center From AI to Big Data to HPC: End-to-end Solutions
Authored by admin Last updated on 10/15/2019 - 17:00
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 10/15/2019 - 19:52