Blog post

Monitoring Intel® Transactional Synchronization Extensions with Intel® PCM

After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol

Authored by Roman Dementiev (Intel) Last updated on 07/04/2019 - 17:00
Blog post

Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).

Authored by Last updated on 07/04/2019 - 17:00
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Authored by Andreas Kleen (Intel) Last updated on 06/07/2017 - 10:53
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Authored by Last updated on 07/06/2019 - 10:52
Blog post

Debug Intel® Transactional Synchronization Extensions

If printf or fprintf functions cause transaction aborts, use Intel® Processor Trace as a work-around.
Authored by Roman Dementiev (Intel) Last updated on 07/04/2019 - 17:00
Blog post

Web Resources About Intel® Transactional Synchronization Extensions

A list useful technical resources related to Intel® Transactional Synchronization Extensions (Intel® TSX)
Authored by Roman Dementiev (Intel) Last updated on 08/30/2019 - 01:53
Article

Intel® Xeon® Processor E7 v3 Product Family

Authored by Nguyen, Khang T (Intel) Last updated on 10/15/2019 - 20:19