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OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Authored by Last updated on 07/31/2019 - 14:30
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Improving Averaging Filter Performance Using Intel® Cilk™ Plus

Intel® Cilk™ Plus is an extension to the C and C++ languages to support data and task parallelism.  It provides three new keywords to i

Authored by Anoop M. (Intel) Last updated on 12/12/2018 - 18:00
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Vectorizing Loops with Calls to User-Defined External Functions

Introduction

Authored by Anoop M. (Intel) Last updated on 12/12/2018 - 18:00
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Disclosure of Hardware Prefetcher Control on Some Intel® Processors

This article discloses the MSR setting that can be used to control the various hardware prefetchers that are available on Intel processors based on the following microarchitectures: Nehalem,

Authored by Vish Viswanathan (Intel) Last updated on 07/05/2019 - 20:34
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部分英特尔处理器硬件预取器的发布

部分英特尔处理器硬件预取器的发布

本文发布的 MST 设置可用来控制基于以下微架构的英特尔处理器上可用的各种硬件预取器: Nehalem、Westmere、Sandy Bridge、Ivy Bridge、Haswell 和 Broadwell。

Authored by Vish Viswanathan (Intel) Last updated on 07/05/2019 - 20:35
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游戏行业的人工智能设计(第一部分)

The gaming industry has seen great strides in game complexity recently. Game developers are challenged to create increasingly compelling games. This series explores important Artificial Intelligence (AI) concepts and how to optimize them for multi-core.
Authored by admin Last updated on 12/12/2018 - 18:00
Article

Fast Gathering-based SpMxV for Linear Feature Extraction

This algorithm can be used to improve sparse matrix-vector and matrix-matrix multiplication in any numerical computation. As we know, there are lots of applications involving semi-sparse matrix computation in High Performance Computing. Additionally, in popular perceptual computing low-level engines, especially speech and facial recognition, semi-sparse matrices are found to be very common....
Authored by Last updated on 12/12/2018 - 18:00
Article

Palestra: Como otimizar seu código sem ser um "ninja" em Computação Paralela

Não perca a palestra "Como otimizar seu código sem ser um "ninja" em Computação Paralela" da Intel que será ministrada durante a Semana sobre Programação Massivamente Paralela em Petrópolis, RJ, no Laboratório Nacional de Computação Científica. Data: 02/02/2016 - 11h30 Local: LNCC - Av. Getúlio Vargas, 333 - Quitandinha - Petrópolis/RJ
Authored by Igor F. (Intel) Last updated on 07/06/2019 - 16:40
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Peel the Onion (Optimization Techniques)

This paper is a more formal response to an Intel® Developer Zone forum posting. See: (https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/590710).
Authored by jimdempseyatthecove (Blackbelt) Last updated on 12/12/2018 - 18:00
Blog post

Reduce Boilerplate Code in Parallelized Loops with C++11 Lambda Expressions

Parallelize loops with Intel® Threading Building Blocks using Intel® C++ Compiler for lambda expressions.
Authored by gaston-hillar (Blackbelt) Last updated on 12/12/2018 - 18:00