Blog post

Monitoring Intel® Transactional Synchronization Extensions with Intel® PCM

After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol

Authored by Roman Dementiev (Intel) Last updated on 07/04/2019 - 17:00
Blog post

Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

Authored by Last updated on 05/28/2018 - 18:30
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Authored by Last updated on 07/06/2019 - 10:52
Article

Intel® Xeon® Processor E7 v3 Product Family

Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Blog post

Exposing Processor Features to Dynamic Languages

Intel® for its part invests countless hours and billions of transistors to add features in our silicon products which will speed up people's lives. If only they knew how to take advantage of it! Part of our job in dynamic languages is what I call "putting the cookies on the bottom shelf". Make this advanced technology easily consumable, and show you the value of it so you can be sure to use it.
Authored by David S. (Blackbelt) Last updated on 07/04/2019 - 19:43
File Wrapper

Parallel Universe Magazine - Issue 17, March 2014

Authored by admin Last updated on 03/21/2019 - 12:00