Filters

Article

Using Multithreaded Libraries to Maximize Performance for Digital Media Apps

Using Multithreaded Libraries to Maximize Performance for Digital Media Apps - Intel® Integrated Performance Primitives (Intel® IPP) is an extensive library of multi-core-ready, highly optimized so

Authored by Paul Steinberg (Intel) Last updated on 06/07/2017 - 10:36
Article

Ubiquitous Parallelism: Earthworm Model

Our model replicates the idea of anatomy of Earthworm to implement Parallelism. Each processor in our model is just like segments of an Earthworm
Authored by Last updated on 03/20/2019 - 13:00
Article

Intel® SDK for OpenCL* Applications - Performance Debugging Intro

To the Intel® OpenCL SDK page

Authored by Maxim Shevtsov (Intel) Last updated on 05/31/2019 - 14:10
Article

Intel® Xeon® Processor E7 v3 Product Family

Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Intel® Xeon® Processor E7-8800/4800 V3 Product Family Technical Overview

Contents

1.     Executive Summary2.     Introduction

Authored by Last updated on 07/06/2019 - 16:40
Article

Intel® Xeon® Processor D Product Family Technical Overview

Contents

1. Form Factor Overview2. Intel® Xeon® Processor D Product Family Overview

Authored by David Mulnix (Intel) Last updated on 07/06/2019 - 16:40
Article

Single-Root Input/Output Virtualization (SR-IOV) with Linux* Containers

This paper is a result of a joint CERN openlab-Intel research activity with the aim to investigate whether Linux Containers can be used together with SR-IOV in conjunction and complementary to the existing virtualization infrastructure in the CERN Data Centre. This solution could be potentially applied to the storage nodes, which are principally used for Input/Output operations, while keeping the...
Authored by Marco Righini (Intel) Last updated on 07/05/2019 - 11:00
Article

采用 Linux* Containers 的单根输入/输出虚拟化 (SR-IOV)

This paper is a result of a joint CERN openlab-Intel research activity with the aim to investigate whether Linux Containers can be used together with SR-IOV in conjunction and complementary to the existing virtualization infrastructure in the CERN Data Centre. This solution could be potentially applied to the storage nodes, which are principally used for Input/Output operations, while keeping the...
Authored by Marco Righini (Intel) Last updated on 07/05/2019 - 11:02
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40