260 Matching Results
Forum topic

Ooops - wrong instruction description in volume 2 of the SDM

Looking at the new version of Volume 2 of the SDM (document 325383-055), I just noticed that the "Description" field for the VINSERTF128 instruction (page 4-514) is incorrect.  It appears to have b

Authored by John D. McCalpin Last updated on 07/02/2015 - 11:39
Forum topic

MPX instructions not in the Appendix A opcode map


Authored by Bea T. Last updated on 07/01/2015 - 14:28

Accelerating Financial Applications on Intel® architecture

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Authored by George Raskulinec (Intel) Last updated on 06/30/2015 - 14:32
Forum topic

Guaranteed atomic operation clarification


I'm trying to understand a line in the Intel Architecture manual. It's a description of a memory operation that is guaranteed to be atomic.

Authored by Nathan P. Last updated on 06/30/2015 - 13:19
Forum topic

Diagnostic 15532: Loop was not vectorized: compile time constraints prevent loop optimization

Product Version: Intel(R) Visual Fortran Compiler XE 15.0 or a later version

Authored by Devorah H. (Intel) Last updated on 06/29/2015 - 20:24
Forum topic

the issue about APIC drop msix interrupt

hello, I have a difficult problem,.scenes are as follows:

the hardware env is Intel(R) Xeon(R) CPU E5-2609 v2 @ 2.50GHz, a Altera FPGA board. 

Authored by wei j. Last updated on 06/28/2015 - 18:27
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