Filters

Article

面向英特尔® 架构优化的 Caffe*:使用现代代码技巧

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Vadim K. (Intel) Last updated on 12/05/2016 - 21:11
Forum topic

_mm_clmulepi64_si128 and pclmulqdq doc error

The operation pseudo code in the intrinsics guid (https://software.intel.com/si

Authored by jimdempseyatthecove Last updated on 12/05/2016 - 13:57
Video

Improving Vectorization Efficiency using Intel® SIMD Data Layout Templates (Intel® SDLT)

Intel® SDLT is a library shipped starting from Intel® C++ Compiler 16.0 Update 1.

Authored by admin Last updated on 12/05/2016 - 13:35
Blog post

From ARM NEON to Intel SSE- the automatic porting solution, tips and tricks

I love ARM. Yes, I do. - Why do I work for Intel then? Because I love Intel even more.

Authored by victoria-zhislina (Intel) Last updated on 12/05/2016 - 08:34
Forum topic

AVX512 On Xeon Phi KNL using Intel Intrinsics

Hi,

I am a newbie to AVX512 Intrinsics, I tried this simple test code on Intel Xeon Phi 7210. I compiled using xMIC_AVX512.

Authored by Mohammad A. Last updated on 11/30/2016 - 13:15
Forum topic

Supported processors for PTWRITE instruction?

I have an i7-6700k processor which does not support the PTWRITE instruction, even though it supports intel processor trace.

Authored by Muhammad Usman N. Last updated on 11/30/2016 - 12:47
Forum topic

AVX-512 in graph process applications

Hello, everyone!

Authored by ilya a. Last updated on 11/29/2016 - 12:28
Article

Using Intel® IPP threaded static libraries

Q: How to get Intel® IPP Static threaded libraries?

Authored by Naveen Gv (Intel) Last updated on 11/28/2016 - 18:05
Forum topic

What is the status of VZEROUPPER use?

The problem with VZEROUPPER comes up again now that the recommendation for the Knights Landing processor is the opposite of previous processors.

Authored by Agner Last updated on 11/25/2016 - 12:22
Article

Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2, AVX-512) and processor-specific optimizations

Explains which Intel® Compiler switches to use to target and optimize for a specific platform, microarchitecture, CPU or processor.
Authored by Martyn Corden (Intel) Last updated on 11/22/2016 - 09:51
For more complete information about compiler optimizations, see our Optimization Notice.