Analyzing Intel® SDE's TSX-related log data for capacity aborts

Authored by HASSAN SALEHE MATAR (Intel)

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Last updated on 01/27/2015 - 08:19

Intel® Software Development Emulator

Authored by Ady Tal (Intel)


Last updated on 04/06/2015 - 05:22

Coarse-grained locks and Transactional Synchronization explained

Authored by James Reinders (Intel)

Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this

Last updated on 10/31/2014 - 15:46

Transactional Synchronization in Haswell

Authored by James Reinders (Intel)

We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”.

Last updated on 06/28/2013 - 16:29

Intel® Software Development Emulator Download

Authored by Ady Tal (Intel)

Intel® Software Development Emulator (released Apr 1, 2015)

Last updated on 04/06/2015 - 05:23

Intel® Software Development Emulator Release Notes

Authored by Ady Tal (Intel)
Release notes for the Intel® Software Development Emulator Last updated on 04/06/2015 - 05:24

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Authored by Roman Dementiev (Intel)

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Last updated on 01/29/2014 - 06:09

Intel(r) Transactional Synchronization Extensions (Intel(r) TSX) profiling with Linux perf

Authored by Andreas Kleen (Intel)

Intel TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler.

Last updated on 05/29/2014 - 09:25

Using HLE and RTM with older compilers with tsx-tools

Authored by Andreas Kleen (Intel)

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Last updated on 06/28/2013 - 16:31

Web Resources about Intel® Transactional Synchronization Extensions

Authored by Roman Dementiev (Intel)

Short URL for this page:

Last updated on 03/19/2015 - 17:24