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Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 15:18
Article

Intel® Xeon Phi™ Processor Applications Performance Proof Points

This presentation is an expanding collection of Intel® Xeon Phi™ processor test cases or “proof points” that demonstrate improved software performance for key

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 16:06
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 4

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel Xeon Phi Coprocessor Workshop: Programming Modeling Part 3

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Gerald M. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 2

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Performance Analysis

This module briefly discusses a performance analysis methodology, collecting HW performance data  and using Intel® VTune Applifier XE to view and interpret the performance data.

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Modeling Part 1

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Optimization Part 2

This module looks at basic optimization techniques for the Intel Xeon Phi coprocessor.

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Optimization Part 1

This module looks at basic optimization techniques for the Intel Xeon Phi coprocessor.

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Advanced Offload Topics Part 3

This module is a more in depth discussion of the offload programming model.

Authored by Mike P. (Intel) Last updated on 09/26/2016 - 13:09
For more complete information about compiler optimizations, see our Optimization Notice.