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采访英特尔® 现代代码开发人员挑战赛特等奖获得者 Mathieu Gravey

Mathieu Gravey 介绍了他的英特尔® 现代代码开发人员挑战赛参赛之旅,以及获得奖品 — CERN openlab 实习机会的喜悦。 在参赛过程中,他将现代代码和基于英特尔至强处理器的并行计算应用于优化大脑模拟代码,并将其性能提升了高达 32,000%。 对于此次实习,他希望与世界顶尖的研究科学家合作实现生物和信息系统的融合。

Authored by tianhui s. Last updated on 05/26/2016 - 18:08
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Part 3: Expressing Parallelism with Vectors

Episode 3 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel architectures” introduces data parallelism and automatic vectorization.

Authored by Last updated on 05/26/2016 - 18:08
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Crash Course on Multi-Threading with OpenMP

Episode 4 of the hands-on workshop (HOW) series on parallel programming and optimization with Intel architectures introduces thread parallelism and the parallel framework OpenMP.

Authored by admin Last updated on 05/26/2016 - 18:08
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Think Parallel Modern Applications for Modern Hardware

HPC codes have used MPI and similar models to scale to multiple nodes, but increasingly parallelism is also required within a node, and even within a single core

Authored by admin Last updated on 05/26/2016 - 18:08
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Optimization of Multi-Threading in Intel® Architectures I

Episode 7 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel architectures” is Part 1 (of 2) of a series on the optimization of multi-threaded applications.

Authored by admin Last updated on 05/26/2016 - 18:08
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The Intel® VTune™ Amplifier XE and the Intel® Math Kernel Library

In Episode 10 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel® architectures” we present additional topics on optimization.

Authored by admin Last updated on 05/26/2016 - 18:08
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Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 4

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/26/2016 - 18:08
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Beginning Intel Xeon Phi Coprocessor Workshop: Programming Modeling Part 3

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Jerry Makare (Intel) Last updated on 05/26/2016 - 18:08
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Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 2

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/26/2016 - 18:08
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Beginning Intel® Xeon Phi™ Coprocessor Workshop: Performance Analysis

This module briefly discusses a performance analysis methodology, collecting HW performance data  and using Intel® VTune Applifier XE to view and interpret the performance data.

Authored by Taylor K. (Intel) Last updated on 05/26/2016 - 18:08
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