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Intel® Perceptual Computing Challenge: Perceptual Pet Demo

Interact with your digital pet in this Intel® Perceptual Computing Challenge Phase 2 entry from Jason Dorris, and learn about the 

Authored by Jerry Makare (Intel) Last updated on 05/03/2016 - 17:58
Video

Head of the Order: Intel® Perceptual Computing Challenge Winners

Head of the Order was the winner of the games catergory of the Intel® Perceptual Computing Challenge Phase 2.

Authored by Jerry Makare (Intel) Last updated on 05/03/2016 - 17:58
Blog post

Ganhadores da primeira fase do Perceptual Challenge Brasil

Authored by Felipe P. (Intel) Last updated on 05/03/2016 - 17:58
Forum topic

contain memory accesses within the enclave?

I'm wondering if it is possible to restrict the enclave code from accessing ordinary memory, namely memory outside of the enclave. This can be a useful feature in general I think.

Authored by Fan Last updated on 05/03/2016 - 17:55
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 4

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/03/2016 - 18:08
Video

Beginning Intel Xeon Phi Coprocessor Workshop: Programming Modeling Part 3

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Jerry Makare (Intel) Last updated on 05/03/2016 - 18:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 2

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/03/2016 - 18:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Performance Analysis

This module briefly discusses a performance analysis methodology, collecting HW performance data  and using Intel® VTune Applifier XE to view and interpret the performance data.

Authored by Taylor K. (Intel) Last updated on 05/03/2016 - 18:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Modeling Part 1

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/03/2016 - 18:08
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