Article

OpenMP* SIMD for Inclusive/Exclusive Scans

The Intel® Compiler 19.0 supports the OpenMP* SIMD SCAN feature for inclusive and exclusive scans.
Authored by Varsha M. (Intel) Last updated on 02/08/2019 - 08:58
Documentation

Intel® C++ Compiler Code Samples from Intel® C++ Compiler Code Samples

Intel® Cilk™ Plus has been deprecated in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics.

Last updated on 03/21/2019 - 09:08
Article

Using Tasks Instead of Threads

Tasks are a lightweight alternative to threads that provide faster startup and shutdown times, better load balancing, an efficient use of available resources, and a higher level of abstraction.
Authored by admin Last updated on 07/05/2019 - 09:41
Article

Set up Offload Over Fabric Software on an Intel® Xeon Phi™ Processor

How to install and enable Offload Over Fabric, configure the hardware, and test the configuration.
Authored by Nguyen, Loc Q (Intel) Last updated on 06/14/2019 - 11:50
Article

Virtual Vector Function Supported in Intel® C++ Compiler 17.0

Intel® C++ Compiler 17.0 starts supporting virtual vector functions.

Authored by Chen, Yuan (Intel) Last updated on 06/01/2017 - 11:32
Article

Multi-core Intermediate

Introduction
Authored by Nguyen, Khang T (Intel) Last updated on 07/13/2018 - 17:29
Documentation

Intel® SIMD Data Layout Templates from Intel® C++ Compiler Code Samples

Intel® SIMD Data Layout Templates (Intel® SDLT) is a template library providing C++ template containers allowing use of an array of "Plain Old Data" (POD) structure that use an in-memory layout to

Last updated on 03/21/2019 - 09:08
Article

Code Sample: Optimizing Binarized Neural Networks on Intel® Xeon® Scalable Processors

In the previous article, we discussed the performance and accuracy of Binarized Neural Networks (BNN). We also introduced a BNN coded from scratch in the Wolfram Language. The key component of this neural network is Matrix Multiplication.
Authored by Yash Akhauri Last updated on 03/21/2019 - 12:40
Article

Explicit Vector Programming in Fortran

No longer does Moore’s Law result in higher frequencies and improved scalar application performance; instead, higher transistor counts lead to increased parallelism, both through more cores and thr

Authored by Martyn Corden (Intel) Last updated on 03/27/2019 - 15:50
Article

Benefits of Intel® Optimized Caffe* in comparison with BVLC Caffe*

Overview
Authored by JON J K. (Intel) Last updated on 05/30/2018 - 07:00