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Recipe: Using Binomial Option Pricing Code as Representative Pricing Derivative Method

Introduction
Authored by Last updated on 03/21/2019 - 12:08
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Recipe: Optimized Caffe* for Deep Learning on Intel® Xeon Phi™ processor x200

The computer learning code Caffe* has been optimized for Intel® Xeon Phi™ processors. This article provides detailed instructions on how to compile and run this Caffe* optimized for Intel® architecture to obtain the best performance on Intel Xeon Phi processors.
Authored by Vamsi Sripathi (Intel) Last updated on 03/21/2019 - 12:40
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Recipe: Building NAMD on Intel® Xeon® and Intel® Xeon Phi™ Processors on a Single Node

This recipe describes a step-by-step process for getting, building, and running NAMD (scalable molecular dynamics code) on the Intel® Xeon Phi™ processor and Intel® Xeon® processor E5 family to achieve better performance.
Authored by Last updated on 07/06/2019 - 16:30
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Recipe: Build NAMD on Intel® Xeon® and Intel® Xeon Phi™ Processors for Multi-node Runs

This recipe describes a step-by-step process for getting, building, and running NAMD (scalable molecular dynamics code) on the Intel® Xeon Phi™ processor and Intel® Xeon® processor family to achieve better performance.
Authored by Last updated on 07/06/2019 - 16:30
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Recipe: Building and Running Soft Sphere Simulation for Intel® Xeon® Processors and Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run the Soft Sphere Simulation sample code with the sample workload on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
Authored by admin Last updated on 09/02/2019 - 15:03
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Recipe: LAMMPS* for Intel® Xeon Phi™ Processors

Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) is a classical molecular dynamics code that can be used to model atoms, or, more generically, as a parallel particle simulator at the atomic, meso, or continuum scale.This code recipe describes how to get, build, and use the LAMMPS* code for the Intel® Xeon Phi™ processor and presents some performance comparisons.
Authored by WILLIAM B. (Intel) Last updated on 09/02/2019 - 15:05
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Optimizing Memory Bandwidth in Knights Landing on Stream Triad

This document demonstrates the best methods to obtain peak memory bandwidth performance on Intel® Xeon Phi™ Processor (codenamed Knights Landing). This is done using STREAM* benchmarks, the de facto industry-standard benchmark for the measurement of computer memory bandwidth.
Authored by Karthik Raman (Intel) Last updated on 09/02/2019 - 15:08
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Recipe: Monte Carlo European Option Pricing for Intel® Xeon Phi® Processor

This article covers the Monte Carlo Methods using a simple quasi random number generator.
Authored by admin Last updated on 09/02/2019 - 15:25
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Recipe: Building and Running MASNUM WAVE for Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run an optimized version of MASNUM WAVE (0.2 degree high resolution) workload on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
Authored by Last updated on 09/02/2019 - 15:27