Article

Intel® Cluster Ready Recipes for StackIQ

Intel® Cluster Ready “recipes” are reference designs provided to help hardware vendors, platform integrators, and system integrators design and build certified Intel Cluster Ready systems. This is a list of all recipes featuring the StackIQ Rocks+* suite.
Authored by admin Last updated on 03/28/2019 - 08:48
Article

Intel® Cluster Ready Recipes for Platform Computing*

Intel® Cluster Ready “recipes” are reference designs provided to help hardware vendors, platform integrators, and system integrators design and build certified Intel Cluster Ready systems. This is a list of all recipes featuring the Platform* suite.
Authored by admin Last updated on 03/28/2019 - 08:48
Article

Intel® Cluster Ready Recipes for OSCAR-Pro*

Intel® Cluster Ready “recipes” are reference designs provided to help hardware vendors, platform integrators, and system integrators design and build certified Intel Cluster Ready systems. This is a list of all recipes featuring the OSCAR-Pro* suite.
Authored by admin Last updated on 03/28/2019 - 08:48
Documentation
Article

Archived - Coding for 2 at Once - Intel RealSense User Facing Cameras

Making applications with Intel RealSense technology compatible with multiple generations of Intel RealSense 3D Cameras (F200 and SR300)
Authored by Last updated on 05/30/2018 - 07:00
Article

Optimizing Memory Bandwidth in Knights Landing on Stream Triad

This document demonstrates the best methods to obtain peak memory bandwidth performance on Intel® Xeon Phi™ Processor (codenamed Knights Landing). This is done using STREAM* benchmarks, the de facto industry-standard benchmark for the measurement of computer memory bandwidth.
Authored by Karthik Raman (Intel) Last updated on 03/21/2019 - 12:00
Article

Recipe: Using Binomial Option Pricing Code as Representative Pricing Derivative Method

Introduction
Authored by Last updated on 03/21/2019 - 12:08
Article

Recipe: Pricing Options Using Barone-Adesi Whaley Approximation

In this paper, we look at one of the successful efforts, pioneered by Barone-Adesi and Whaley, and apply the high performance parallel computing entailed in the modern microprocessors to create a program that can exceed our expectation for high performance with a suitable numerical result.
Authored by admin Last updated on 03/21/2019 - 12:00
Article

Recipe: Optimized Caffe* for Deep Learning on Intel® Xeon Phi™ processor x200

The computer learning code Caffe* has been optimized for Intel® Xeon Phi™ processors. This article provides detailed instructions on how to compile and run this Caffe* optimized for Intel® architecture to obtain the best performance on Intel Xeon Phi processors.
Authored by Vamsi Sripathi (Intel) Last updated on 03/21/2019 - 12:40