Documentation

OpenMP* Code Analysis Method from Intel® VTune™ Amplifier Performance Analysis Cookbook

This recipe introduces a flow to analyze CPU utilization of your OpenMP* or hybrid OpenMP-MPI application and identify causes of possible inefficiencies.

Last updated on 06/07/2019 - 03:40
Documentation

OpenMP* Imbalance and Scheduling Overhead from Intel® VTune™ Amplifier Performance Analysis Cookbook

This recipe shows how to detect and fix frequent parallel bottlenecks of OpenMP programs such as imbalance on barriers and scheduling overhead.

Last updated on 06/07/2019 - 03:40
Documentation

Processor Cores Underutilization: OpenMP* Serial Time from Intel® VTune™ Amplifier Performance Analysis Cookbook

This recipe shows how to identify a fraction of serial execution in an application parallelized with OpenMP, discover additional opportunities for parallelization, and improve scalability of the application.

Last updated on 06/07/2019 - 03:40
Documentation

Methodologies from Intel® VTune™ Amplifier Performance Analysis Cookbook

Start cooking your performance analysis with understanding tuning techniques, performance metrics and hardware solutions for collecting statistics. After that you can drill down to particular tuning or configuration recipes provided for the Intel® VTune™ Amplifier.

Last updated on 06/07/2019 - 03:40
Documentation

Tuning Recipes from Intel® VTune™ Amplifier Performance Analysis Cookbook

These recipes explore the most typical performance problems that can be detected with the Intel® VTune™ Amplifier and provide possible steps for the performance optimization.

Last updated on 06/07/2019 - 03:40
Documentation

Inefficient Synchronization from Intel® VTune™ Amplifier Performance Analysis Cookbook

This recipe shows how to locate inefficient synchronization in your code by running the Advanced Hotspots analysis of the Intel® VTune™ Amplifier with the stack collection enabled.

Last updated on 06/07/2019 - 03:40
Article

Recipe: Building and Running Soft Sphere Simulation for Intel® Xeon® Processors and Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run the Soft Sphere Simulation sample code with the sample workload on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
Authored by admin Last updated on 06/14/2019 - 11:50
Article

Recipe: Building and Running YASK (Yet Another Stencil Kernel) on Intel® Processors

Yet Another Stencil Kernel (YASK), is a framework to facilitate design exploration and tuning of HPC kernels including vector folding, cache blocking, memory layout, loop construction, temporal wave-front blocking, and others.YASK contains a specialized source-to-source translator to convert scalar C++ stencil code to SIMD-optimized code.
Authored by Chuck Yount (Intel) Last updated on 03/21/2019 - 12:00
Article

Recipe: Building and Running GROMACS* on Intel® Processors

This recipe describes how to get, build, and run the GROMACS* code on Intel® Xeon® and Intel® Xeon Phi™ processors for better performance on a single node.
Authored by Smahane Douyeb. (Intel) Last updated on 03/21/2019 - 12:08
Documentation

Profiling MPI Applications from Intel® VTune™ Amplifier Performance Analysis Cookbook

This recipe uses Intel® VTune™ Amplifier to identify imbalances and communications issues in MPI enabled applications, allowing you to improve the application performance.

Last updated on 06/07/2019 - 03:40