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Intel® IPP - Threading / OpenMP* FAQ

This page contains common questions and answers on multi-threading in the Intel IPP.
Authored by Last updated on 07/31/2019 - 14:30
Article

Intel® IPP - Library dependencies by domain

IPP demain dependencies.
Authored by admin Last updated on 07/31/2019 - 14:30
Article

Intel® IPP Functions Optimized for Intel® Advanced Vector Extensions 2 (Intel® AVX2)

List of Intel IPP functions optimized for processor code name Haswell and Skylake
Authored by Shaojuan Z. (Intel) Last updated on 07/31/2019 - 14:30
Article

Intel® Node Manager Programmer’s Reference Kit

Intel® Node Manager is a server management technology that allows a platform's management software to accurately monitor and control the platform's power and thermal behaviors through an industry-d

Authored by Last updated on 07/05/2019 - 20:37
Article

Intel® Xeon® Phi™ Processor Performance Monitoring Reference Manual

The Intel® Xeon® Phi™ Processor (code name Knights Landing) provides performance monitoring facilities that are a unique combination of Intel® Atom™ processor-like core performance monitoring units (PMU) and Intel® Xeon® processor based server class uncore capabilities.
Authored by Last updated on 07/29/2019 - 07:45
Blog post

Deprecating the PCOMMIT Instruction

The PCOMMIT instruction has been deprecated.
Authored by Rudoff, Andy M (Intel) Last updated on 07/04/2019 - 19:20
Video

Optimizing Torch Performance for Intel® Xeon Phi Processor Webinar

Learn how machine learning/deep learning applications benefit from code modernization.

Authored by Last updated on 03/21/2019 - 12:40
Article

Intel® Xeon® Processor Scalable Family Technical Overview

The new generation, the Intel® Xeon® processor Scalable family (formerly code-named Skylake-SP), is based on 14nm process technology, with many new and enhanced architecture changes including, Skylake Mesh Architecture and Intel® Advanced Vector Extensions 512 (Intel® AVX-512).
Authored by David Mulnix (Intel) Last updated on 07/06/2019 - 16:30