Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Authored by Last updated on 07/31/2019 - 14:30
Blog post

Debug Intel® Transactional Synchronization Extensions

If printf or fprintf functions cause transaction aborts, use Intel® Processor Trace as a work-around.
Authored by Roman Dementiev (Intel) Last updated on 07/04/2019 - 17:00
Article

Fast Computation of Adler32 Checksums

Adler32 is a common checksum used for checking the integrity of data in applications such as zlib*, a popular compression library. In this paper we show how the vector processing capabilities of Intel® Architecture Processors can be exploited to efficiently compute the Adler32 checksum.
Authored by James Guilford (Intel) Last updated on 12/12/2018 - 18:00
Blog post

Track Reconstruction with Deep Learning at the CERN CMS Experiment

Connecting the Dots
Authored by Last updated on 12/12/2018 - 18:00
Blog post

Cells in the Cloud: Scaling a Biological Simulator to the Cloud

Hello, fellow developers! I am Konstantinos, and I currently work at CERN as a research intern for this summer.

Authored by Konstantinos Kanellis Last updated on 12/12/2018 - 18:00
Blog post

Cells in the Cloud: Distributed Runtime Prototype Implementation

Hello, everyone!

Authored by Konstantinos Kanellis Last updated on 12/12/2018 - 18:00
Blog post

Superior kdb+* Performance on Intel® Xeon Phi™ Product Family

The Intel®  Xeon Phi™ product family shares the same architecture, I

Authored by Last updated on 09/30/2019 - 16:50
Blog post

Track Reconstruction with Deep Learning at the CERN CMS Experiment

This blog post is part of a series that describes my summer school project at CERN openlab.

Authored by Last updated on 09/30/2019 - 16:50
Article

Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:28
Article

Direct N-body Simulation

Exercise in performance optimization on Intel Architecture, including Intel® Xeon Phi™ processors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:28