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OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Authored by Last updated on 06/23/2019 - 18:50
Article

OpenMP* 5.0 support in Intel® Compiler 18.0

OpenMP 5.0 is the next version of the OpenMP specification which should be officially released in 2018.

Authored by Igor V. (Intel) Last updated on 03/09/2019 - 12:30
Article

Scale-Up Implementation of a Transportation Network Using Ant Colony Optimization (ACO)

In this article an OpenMP* based implementation of the Ant Colony Optimization algorithm was analyzed for bottlenecks with Intel® VTune™ Amplifier XE 2016 together with improvements using hybrid MPI-OpenMP and Intel® Threading Building Blocks were introduced to achieve efficient scaling across a four-socket Intel® Xeon® processor E7-8890 v4 processor-based system.
Authored by Sunny G. (Intel) Last updated on 07/05/2019 - 19:10
Article

Fine-Tuning Optimization for a Numerical Method for Hyperbolic Equations Applied to a Porous Media Flow Problem with Intel® Tools

This paper presents an analysis for potential optimization for a Godunov-type semi-discrete central scheme, for a particular hyperbolic problem implicated in porous media flow, using OpenMP* and Intel® Advanced Vector Extensions 2.
Authored by Last updated on 07/03/2019 - 20:00
Article

Set up Offload Over Fabric Software on an Intel® Xeon Phi™ Processor

How to install and enable Offload Over Fabric, configure the hardware, and test the configuration.
Authored by Nguyen, Loc Q (Intel) Last updated on 06/14/2019 - 11:50
Article

Maximize TensorFlow* Performance on CPU: Considerations and Recommendations for Inference Workloads

This article will describe performance considerations for CPU inference using Intel® Optimization for TensorFlow*
Authored by Nathan Greeneltch (Intel) Last updated on 04/01/2019 - 13:01
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 07/06/2019 - 16:40
Article

Building and Probing Prolog* with Intel® Architecture

This article explores what happens when Intel solutions support functional and logic programming languages that are regularly used for Artificial Intelligence (AI) and proposes a Prolog interpreter recompilation using Intel® C++ Compiler and libraries in order to evaluate their contribution to logic based AI.
Authored by Flavio Luis de Mello Last updated on 01/24/2018 - 15:35
Article

Intel® Cluster Tools in a Cray* Environment, Part 1

Purpose
Authored by Mark L. (Intel) Last updated on 07/06/2019 - 11:24
Article

Recipe: Building and Running YASK (Yet Another Stencil Kernel) on Intel® Processors

Yet Another Stencil Kernel (YASK), is a framework to facilitate design exploration and tuning of HPC kernels including vector folding, cache blocking, memory layout, loop construction, temporal wave-front blocking, and others.YASK contains a specialized source-to-source translator to convert scalar C++ stencil code to SIMD-optimized code.
Authored by Chuck Yount (Intel) Last updated on 03/21/2019 - 12:00