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Code Sample: Exploring MPI for Python* on Intel® Xeon Phi™ Processor

Learn how to write an MPI program in Python*, and take advantage of Intel® multicore architectures using OpenMP threads and Intel® AVX512 instructions.
Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 16:30
Article

Set up Offload Over Fabric Software on an Intel® Xeon Phi™ Processor

How to install and enable Offload Over Fabric, configure the hardware, and test the configuration.
Authored by Nguyen, Loc Q (Intel) Last updated on 06/14/2019 - 11:50
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 07/06/2019 - 16:40
Article

Case Study: Many-Fermion Dynamics using Intel® Xeon Phi™ Processors

Many-Fermion Dynamics---nuclear, or MFDn, is a configuration interaction (CI) code for nuclear structure calculations.

Authored by Mike P. (Intel) Last updated on 06/14/2019 - 11:50
Article

Recipe: Building and Running YASK (Yet Another Stencil Kernel) on Intel® Processors

Yet Another Stencil Kernel (YASK), is a framework to facilitate design exploration and tuning of HPC kernels including vector folding, cache blocking, memory layout, loop construction, temporal wave-front blocking, and others.YASK contains a specialized source-to-source translator to convert scalar C++ stencil code to SIMD-optimized code.
Authored by Chuck Yount (Intel) Last updated on 03/21/2019 - 12:00
Article

Thread Parallelism in Cython*

Cython* is a superset of Python* that additionally supports C functions and C types on variable and class attributes. Cython generates C extension modules, which can be used by the main Python program using the import statement.
Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 16:30
Article

Improve Application Performance on an Intel® Xeon Phi™ Processor

Learn techniques for vectorizing code, adding thread-level parallelism, and enabling memory optimization.
Authored by Nguyen, Loc Q (Intel) Last updated on 06/14/2019 - 11:50
Article

Recipe: Building and Running GROMACS* on Intel® Processors

This recipe describes how to get, build, and run the GROMACS* code on Intel® Xeon® and Intel® Xeon Phi™ processors for better performance on a single node.
Authored by Smahane Douyeb. (Intel) Last updated on 03/21/2019 - 12:08
Article

Performance of Classic Matrix Multiplication Algorithm on Intel® Xeon Phi™ Processor System

Matrix multiplication (MM) of two matrices is one of the most fundamental operations in linear algebra. The algorithm for MM is very simple, it could be easily implemented in any programming language. This paper shows that performance significantly improves when different optimization techniques are applied.
Authored by Last updated on 06/14/2019 - 11:50
Article

Intel® Xeon Phi™ Processor 7200 Family Memory Management Optimizations

This paper examines software performance optimization for an implementation of a non-library version of DGEMM executing on the Intel® Xeon Phi™ processor (code-named Knights Landing, with acronym K

Authored by Last updated on 07/06/2019 - 16:30