Blog post

About the pain of parallel programming

If you’ve ever heard about parallel programming it probably sounded like a painful endeavor.

Authored by Frank Schlimbach (Intel) Last updated on 08/15/2016 - 12:59
Blog post

Announcing Intel Concurrent Collections for Haskell 0.1

Hello Parallel Programmers!

Authored by Last updated on 08/15/2016 - 12:54
Blog post

CLRS III: Extension of the Threads

I've got a great wife. For my birthday she got me a copy of the newly updated Introduction to Algorithms, 3rd ed. by Cormen, Leiserson, Rivest, and Stein.

Authored by Clay B. Last updated on 08/15/2016 - 12:48
Blog post

Tips and Tricks when working with Intel® TXT

I've recently started learning about Intel® Trusted Execution Technology (Intel® TXT).

Authored by Colleen C. (Intel) Last updated on 08/15/2016 - 12:47
Blog post

VMware Fusion 5 supports Intel® VTune™ Amplifier event sampling

One of the great features in Intel® VTune™ Amplifier is the use of the event monitoring registers built into Intel processors.

Authored by James R. Last updated on 06/06/2016 - 15:23
Blog post

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Authored by Roman Dementiev (Intel) Last updated on 04/26/2016 - 10:38
Blog post

Compete And Win A Prize With The New Intel® CnC!

A new version if Intel®

Authored by Frank Schlimbach (Intel) Last updated on 04/08/2016 - 17:38
Blog post

PLDI Tutorial on Intel® Array Building Blocks, a dynamic compiler for data-parallel heterogeneous systems

The Conference on Programming Language Design and Implementation (PLDI), June 4-8, 2011, in San Jose, CA features a half-day tutorial that I’ll be giving on Intel® Array Building Blocks, which is a

Authored by CJ Newburn (Intel) Last updated on 07/31/2013 - 09:03
For more complete information about compiler optimizations, see our Optimization Notice.