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Submissions open: High Performance Parallelism Gems

We have all had our little discoveries and triumphs in identifying new and innovative approaches that increased the performance of our applications. Occasionally we find something more, something that could also help others, an innovative gem. You now have an opportunity to broadcast your successes more widely to the benefit of our community. You are invited to submit a proposal to a...
Authored by Taylor K. (Intel) Last updated on 07/28/2015 - 15:03
Blog post

The Chronicles of Phi - part 5 - Plesiochronous phasing barrier – tiled_HT3

For the next optimization, I knew what I wanted to do; I just didn’t know what to call it. In looking for words that describes loosely-synchronous, I came across plesiochronous:

Authored by jimdempseyatthecove Last updated on 07/28/2015 - 15:03
Blog post

Finding the right fit for your application on Intel® Xeon and Intel® Xeon Phi™ processors

Not all applications are created equal.   Some are chomping at the bit to harvest as much parallelism as a target platform can provide.  Those may be good candidates for running on an Intel®

Authored by CJ Newburn (Intel) Last updated on 07/28/2015 - 15:03
Blog post

AVX-512 instructions

Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

Authored by James Reinders (Intel) Last updated on 07/23/2015 - 13:23
Blog post

The Chronicles of Phi - part 4 - Hyper-Thread Phalanx – tiled_HT2

The prior part (3) of this blog showed the effects of the first-level implementation of the Hyper-Thread Phalanx.

Authored by jimdempseyatthecove Last updated on 07/21/2015 - 17:57
Blog post

The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and...
Authored by jimdempseyatthecove Last updated on 07/21/2015 - 17:57
Blog post

The Chronicles of Phi - part 2 Hyper-Thread Phalanx – tiled_HT1

Strategy to address the performance issue through use of a Hyper-Thread Phalanx.
Authored by jimdempseyatthecove Last updated on 07/21/2015 - 17:57
Blog post

The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued

The prior part (2) of this blog provided a header and set of function that

Authored by jimdempseyatthecove Last updated on 07/21/2015 - 17:57
Blog post

Check out the Parallel Universe e-publication

The Parallel Universe is a quarterly publication devoted to exploring inroads and innovations in the field of software development, from high performance computing to threading hybrid applications.

Authored by Mike Pearce (Intel) Last updated on 07/21/2015 - 11:31
Blog post

Intel® Inspector XE 2013: автоматическая верификация и отладка в реальном времени

Тестирование и поиск ошибок – неотъемлемая и не самая интересная часть процесса разработки ПО. Для избавления себя от рутины этот процесс все стараются автоматизировать.

Authored by Kirill Rogozhin (Intel) Last updated on 07/21/2015 - 11:31
For more complete information about compiler optimizations, see our Optimization Notice.