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Submissions open: High Performance Parallelism Gems

We have all had our little discoveries and triumphs in identifying new and innovative approaches that increased the performance of our applications. Occasionally we find something more, something that could also help others, an innovative gem. You now have an opportunity to broadcast your successes more widely to the benefit of our community. You are invited to submit a proposal to a...
Authored by Taylor K. (Intel) Last updated on 08/01/2015 - 18:03
Blog post

What’s New in Intel® Composer XE 2013 SP1

Intel® Composer XE 2013 SP1 includes Intel® Compiler 14.0 among other components.

Authored by loc-nguyen (Intel) Last updated on 08/01/2015 - 18:03
Blog post

The Chronicles of Phi - part 5 - Plesiochronous phasing barrier – tiled_HT3

For the next optimization, I knew what I wanted to do; I just didn’t know what to call it. In looking for words that describes loosely-synchronous, I came across plesiochronous:

Authored by jimdempseyatthecove Last updated on 08/01/2015 - 18:03
Blog post

Finding the right fit for your application on Intel® Xeon® and Intel® Xeon Phi™ processors

Not all applications are created equal.   Some are chomping at the bit to harvest as much parallelism as a target platform can provide.  Those may be good candidates for running on an Intel®

Authored by CJ Newburn (Intel) Last updated on 08/01/2015 - 18:03
Blog post

Parallel Universe Magazine #12: Advanced Vectorization

This blog contains additional content for the article "Advanced Vectorization" from Parallel Universe #12:

Authored by Georg Zitzlsberger (Intel) Last updated on 08/01/2015 - 18:03
Blog post

Why #AWE2015 Was AWEsome!

So Intel was at Augmented World Expo 2015. Why? And what did we do there and what did we share? Read this blog to find out!
Authored by CaptGeek (Intel) Last updated on 07/31/2015 - 12:03
Blog post

Women in Technology in México and Argentina

Intel Argentina and Intel Mexico both organized and executed the first developer events that were 100% dedicated to women in their countries. Both events kicked-off technical training series that will start in Q3.
Authored by MATTHEW H. (Intel) Last updated on 07/31/2015 - 09:39
Blog post

The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued

The prior part (2) of this blog provided a header and set of function that

Authored by jimdempseyatthecove Last updated on 07/30/2015 - 15:25
Blog post

The Chronicles of Phi - part 2 Hyper-Thread Phalanx – tiled_HT1

Strategy to address the performance issue through use of a Hyper-Thread Phalanx.
Authored by jimdempseyatthecove Last updated on 07/30/2015 - 15:24
Blog post

The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and...
Authored by jimdempseyatthecove Last updated on 07/30/2015 - 15:23
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