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Optimization of Data Read/Write in a Parallel Application

(This work was done by Vivek Lingegowda during his internship at Intel.)

Authored by Last updated on 07/04/2019 - 17:40
Article

用于亚洲期权定价的 Monte Carlo 模拟

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:30
Article

Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:28
Article

基于英特尔® 架构加速金融应用

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Authored by George Raskulinec (Intel) Last updated on 10/03/2019 - 08:00
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Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 10/15/2019 - 19:52
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Accelerating Financial Applications on Intel® architecture

Learn more about an in-depth analysis of code modernization performance conducted by optimizing original CPU code and re-running tests on the latest GPU/CPU hardware.
Authored by George Raskulinec (Intel) Last updated on 10/17/2019 - 14:37