Article

Maximize TensorFlow* Performance on CPU: Considerations and Recommendations for Inference Workloads

This article will describe performance considerations for CPU inference using Intel® Optimization for TensorFlow*
Authored by Nathan Greeneltch (Intel) Last updated on 07/31/2019 - 12:11
Article

A Tutorial on the C++ API of Intel® Data Analytics Acceleration Library

Intel® DAAL is a part of Intel® Parallel Studio XE 2016, a developer toolkit for HPC and technical computing applications. Intel® DAAL is a powerful library for big data developers that turns large data clusters into meaningful information with advanced analytics algorithms. In this tutorial, we will see how to build and run Intel® DAAL C++ examples included in the package.
Authored by Zhang, Zhang (Intel) Last updated on 08/27/2019 - 13:50
Article

Free access to Intel® Compilers, Performance libraries, Analysis tools and more...

Intel® Parallel Studio XE is a very popular product from Intel that includes the Intel® Compilers, Intel® Performance Libraries, tools for analysis, debugging and tuning, tools for MPI and the Intel® MPI Library. Did you know that some of these are available for free? Here is a guide to “what is available free” from the Intel Parallel Studio XE suites.
Authored by admin Last updated on 09/30/2019 - 17:28
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 10/15/2019 - 15:30
Article

Intel Solutions and Technologies for the Evolving Data Center

  One Stop for Optimizing Your Data Center From AI to Big Data to HPC: End-to-end Solutions
Authored by admin Last updated on 10/15/2019 - 17:00
Blog post

Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

Authored by gaston-hillar (Blackbelt) Last updated on 10/15/2019 - 17:38
Blog post

Doubling the Performance of OpenStack Swift* with No Code Changes

My current gig is mostly about performance. I manage a group of software engineers dedicated to the languages becoming really important to the cloud and the datacenter.

Authored by David S. (Blackbelt) Last updated on 10/15/2019 - 19:31
Blog post

The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Authored by David S. (Blackbelt) Last updated on 10/15/2019 - 19:42
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 10/15/2019 - 19:52