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Advanced Computer Concepts for the (Not So) Common Chef: The Multi-core Industrial Kitchen

This is going to be a short blog as there is no new material to discuss, just a simple extension of the earlier blogs (see

Authored by taylor k. Last updated on 07/20/2016 - 09:04
Blog post

Webinar: Programmer's Guide to Knights Landing

The Intel’s next generation Xeon Phi™ processor family x200 product (code-name Knights Landing) brings in several new technological solutions: socket form-factor (stand-alone CPU), as well as coprocessor version; a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in addition to the traditional DDR4, which leads to three modes of MCDRAM operation - cache, flat, and hybrid;...
Authored by Vadim K. (Intel) Last updated on 07/13/2016 - 11:02
Blog post

Reducing boilerplate code in parallelized loops with C++11 lambda expressions

The C++11 standard, formerly known as C++0x, brought lambda expressions, and their usage greatly reduces boilerplate code. Intel® C++ compiler allows us to take advantage of lambda expressions to reduce boilerplate code when parallelizing loops with Intel® Threading Building Blocks (Intel® TBB).
Authored by gaston-hillar Last updated on 07/13/2016 - 11:01
Blog post

Can You Write a Vectorized Reduction Operation?

I can. And if you read this post you will also be able to write one, too. (Might be a cool party trick or a sucker bet to make a little cash.)
Authored by Clay B. Last updated on 07/13/2016 - 10:56
Blog post

Vectorized Reduction 2: Let the Compiler do that Voodoo that it do so well

As I mentioned in my previous post about writing a vectorized reduction code from Intel vector intrinsics, that part of the code was just the finishing touch on a loop computing squared difference of complex values.
Authored by Clay B. Last updated on 07/13/2016 - 10:53
Blog post

A Guide to Optimization Techniques for the Intel® MIC Architecture

A 3-part educational series on Optimization Techniques for the Intel® MIC Architecture is provided by Colfax Research. The series focuses on select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon® processors and Intel® Xeon Phi™ processors).
Authored by Iman Saleh (Intel) Last updated on 07/12/2016 - 11:00
Blog post

Reducing Initialization Times of the Intel MPI® Library

Running large scale Intel® MPI applications on InfiniBand* clusters, one might have recognized an increasing time spend within the MPI_Init() routine.

Authored by Michael Steyer (Intel) Last updated on 07/12/2016 - 10:45
Blog post

Free Online Training on Parallel Programming and Optimization

The Colfax Hands On Workshop (HOW) training series is an integral part of the Intel Modern Code Developer program which supports developers in leveraging application performance in code through a systematic optimization methodology. Attendees of these workshops may receive a certificate of completion. The certificate states the Fundamental level of accomplishment in the Parallel Programming Track...
Authored by Mike P. (Intel) Last updated on 07/11/2016 - 09:00
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Teaching Parallelism at SIGCSE 2011- See the booth demo videos, session talks, and professor interviews!

The Intel Academic Community had a fantastic time engaging with computer science educators at SIGCSE 2011!

Authored by Last updated on 07/06/2016 - 21:48
For more complete information about compiler optimizations, see our Optimization Notice.