Blog post

Optimization of Data Read/Write in a Parallel Application

(This work was done by Vivek Lingegowda during his internship at Intel.)

Authored by Last updated on 07/04/2019 - 17:40
Article

Multithreaded Code Optimization in PARSEC* 3.0: BlackScholes

Learn about the Blach-Scholes benchmark, part of the benchmark suite of multithreaded programs that comprise the Princeton Application Repository for Shared-Memory Computers (PARSEC).
Authored by Artem G. (Intel) Last updated on 07/04/2019 - 21:42
File Wrapper

White Paper: Creating Trust in the Cloud

Authored by Dan Fineberg (Intel) Last updated on 08/30/2019 - 08:08
Article

Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Authored by Mike P. (Intel) Last updated on 09/30/2019 - 17:28
Article

Case Study: Achieving High Performance on Monte Carlo European Option Using Stepwise Optimization Framework

Read this case study that discusses the Monte Carlo method of statistical computing to solve complex scientific computing problems.
Authored by Last updated on 10/03/2019 - 08:02
Article

Vector API Developer Program for Java* Software

This article introduces Vector API to Java* developers. It shows how to start using the API in Java programs, and provides examples of vector algorithms. It provides step-by-step details on how to build the Vector API and build Java applications using it. It provides the location for downloadable binaries for Project Panama binaries.
Authored by Neil V. (Intel) Last updated on 10/15/2019 - 15:30
Article
Article

Monte Carlo Method for Stock Options Pricing Sample

Download for Windows*

Authored by Last updated on 10/15/2019 - 16:50
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 10/15/2019 - 19:52