Article

Scale-Up Implementation of a Transportation Network Using Ant Colony Optimization (ACO)

In this article an OpenMP* based implementation of the Ant Colony Optimization algorithm was analyzed for bottlenecks with Intel® VTune™ Amplifier XE 2016 together with improvements using hybrid MPI-OpenMP and Intel® Threading Building Blocks were introduced to achieve efficient scaling across a four-socket Intel® Xeon® processor E7-8890 v4 processor-based system.
Authored by Sunny G. (Intel) Last updated on 07/05/2019 - 19:10
Article

Missing lsb dependency when installing Intel® Cluster Runtimes on SLES* 12

How to resolve a missing lsb package on SLES* 12.
Authored by Jeremy Siadal (Intel) Last updated on 07/06/2019 - 11:34
Article

FAT Binary Created for Windows* Static (.lib) and Dynamic-Link (.dll) Library Containing Intel® Xeon Phi™ Coprocessor Offload Code

The Intel® Parallel Studio XE 2015 Composer Editions for Windows* have an internal implementation feature enhancement enabling the Intel® 15.0 compilers to create a FAT binary file for the Windows*

Authored by Last updated on 06/14/2019 - 14:36
Blog post

Modernizing Software with Future-Proof Code Optimizations

by Henry A. Gabb, Sr. Principal Engineer, Intel Software and Services Group

Authored by Henry Gabb (Intel) Last updated on 07/06/2019 - 17:10
Article

ELF Executable Binary File Created for the Intel® Xeon Phi™ Coprocessor Offload Image

The Intel® Parallel Studio XE 2015 Composer Editions for Windows* and Linux* have an internal implementation feature enhancement to the Intel® Xeon Phi™ coprocessor binary image created when using

Authored by Last updated on 06/14/2019 - 13:56
Article

Understanding NUMA for 3D Isotropic Finite Difference (3DFD) Wave Equation Code

This article demonstrates techniques that software developers can use to identify and fix NUMA-related performance issues in their applications.
Authored by Sunny G. (Intel) Last updated on 07/05/2019 - 20:12
Article

Using Intel® VTune™ Amplifier on Cray* XC systems

Introduction

Authored by vladimir-tsymbal (Intel) Last updated on 07/04/2019 - 21:36
Article

Tuning SIMD vectorization when targeting Intel® Xeon® Processor Scalable Family

Introduction

The Intel® Xeon® Processor Scalable Family is based on the server microarchitecture codenamed Skylake.

Authored by J.D. Patel (Intel) Last updated on 05/10/2019 - 08:30
Article

Offload Computations from Servers with an Intel® Xeon Phi™ Processor

Learn how to use Offload over Fabric software for a server migration path.
Authored by Jan Z. (Intel) Last updated on 07/06/2019 - 16:40